1 /*
2  * Copyright 2013 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include <subdev/clk.h>
25 #include "pll.h"
26 
27 #include <subdev/timer.h>
28 #include <subdev/bios.h>
29 #include <subdev/bios/pll.h>
30 
31 struct gk104_clk_info {
32 	u32 freq;
33 	u32 ssel;
34 	u32 mdiv;
35 	u32 dsrc;
36 	u32 ddiv;
37 	u32 coef;
38 };
39 
40 struct gk104_clk {
41 	struct nvkm_clk base;
42 	struct gk104_clk_info eng[16];
43 };
44 
45 static u32 read_div(struct gk104_clk *, int, u32, u32);
46 static u32 read_pll(struct gk104_clk *, u32);
47 
48 static u32
49 read_vco(struct gk104_clk *clk, u32 dsrc)
50 {
51 	struct nvkm_device *device = clk->base.subdev.device;
52 	u32 ssrc = nvkm_rd32(device, dsrc);
53 	if (!(ssrc & 0x00000100))
54 		return read_pll(clk, 0x00e800);
55 	return read_pll(clk, 0x00e820);
56 }
57 
58 static u32
59 read_pll(struct gk104_clk *clk, u32 pll)
60 {
61 	struct nvkm_device *device = clk->base.subdev.device;
62 	u32 ctrl = nvkm_rd32(device, pll + 0x00);
63 	u32 coef = nvkm_rd32(device, pll + 0x04);
64 	u32 P = (coef & 0x003f0000) >> 16;
65 	u32 N = (coef & 0x0000ff00) >> 8;
66 	u32 M = (coef & 0x000000ff) >> 0;
67 	u32 sclk;
68 	u16 fN = 0xf000;
69 
70 	if (!(ctrl & 0x00000001))
71 		return 0;
72 
73 	switch (pll) {
74 	case 0x00e800:
75 	case 0x00e820:
76 		sclk = device->crystal;
77 		P = 1;
78 		break;
79 	case 0x132000:
80 		sclk = read_pll(clk, 0x132020);
81 		P = (coef & 0x10000000) ? 2 : 1;
82 		break;
83 	case 0x132020:
84 		sclk = read_div(clk, 0, 0x137320, 0x137330);
85 		fN   = nvkm_rd32(device, pll + 0x10) >> 16;
86 		break;
87 	case 0x137000:
88 	case 0x137020:
89 	case 0x137040:
90 	case 0x1370e0:
91 		sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
92 		break;
93 	default:
94 		return 0;
95 	}
96 
97 	if (P == 0)
98 		P = 1;
99 
100 	sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
101 	return sclk / (M * P);
102 }
103 
104 static u32
105 read_div(struct gk104_clk *clk, int doff, u32 dsrc, u32 dctl)
106 {
107 	struct nvkm_device *device = clk->base.subdev.device;
108 	u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
109 	u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
110 
111 	switch (ssrc & 0x00000003) {
112 	case 0:
113 		if ((ssrc & 0x00030000) != 0x00030000)
114 			return device->crystal;
115 		return 108000;
116 	case 2:
117 		return 100000;
118 	case 3:
119 		if (sctl & 0x80000000) {
120 			u32 sclk = read_vco(clk, dsrc + (doff * 4));
121 			u32 sdiv = (sctl & 0x0000003f) + 2;
122 			return (sclk * 2) / sdiv;
123 		}
124 
125 		return read_vco(clk, dsrc + (doff * 4));
126 	default:
127 		return 0;
128 	}
129 }
130 
131 static u32
132 read_mem(struct gk104_clk *clk)
133 {
134 	struct nvkm_device *device = clk->base.subdev.device;
135 	switch (nvkm_rd32(device, 0x1373f4) & 0x0000000f) {
136 	case 1: return read_pll(clk, 0x132020);
137 	case 2: return read_pll(clk, 0x132000);
138 	default:
139 		return 0;
140 	}
141 }
142 
143 static u32
144 read_clk(struct gk104_clk *clk, int idx)
145 {
146 	struct nvkm_device *device = clk->base.subdev.device;
147 	u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));
148 	u32 sclk, sdiv;
149 
150 	if (idx < 7) {
151 		u32 ssel = nvkm_rd32(device, 0x137100);
152 		if (ssel & (1 << idx)) {
153 			sclk = read_pll(clk, 0x137000 + (idx * 0x20));
154 			sdiv = 1;
155 		} else {
156 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
157 			sdiv = 0;
158 		}
159 	} else {
160 		u32 ssrc = nvkm_rd32(device, 0x137160 + (idx * 0x04));
161 		if ((ssrc & 0x00000003) == 0x00000003) {
162 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
163 			if (ssrc & 0x00000100) {
164 				if (ssrc & 0x40000000)
165 					sclk = read_pll(clk, 0x1370e0);
166 				sdiv = 1;
167 			} else {
168 				sdiv = 0;
169 			}
170 		} else {
171 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
172 			sdiv = 0;
173 		}
174 	}
175 
176 	if (sctl & 0x80000000) {
177 		if (sdiv)
178 			sdiv = ((sctl & 0x00003f00) >> 8) + 2;
179 		else
180 			sdiv = ((sctl & 0x0000003f) >> 0) + 2;
181 		return (sclk * 2) / sdiv;
182 	}
183 
184 	return sclk;
185 }
186 
187 static int
188 gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
189 {
190 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
191 	struct nvkm_device *device = clk->base.subdev.device;
192 
193 	switch (src) {
194 	case nv_clk_src_crystal:
195 		return device->crystal;
196 	case nv_clk_src_href:
197 		return 100000;
198 	case nv_clk_src_mem:
199 		return read_mem(clk);
200 	case nv_clk_src_gpc:
201 		return read_clk(clk, 0x00);
202 	case nv_clk_src_rop:
203 		return read_clk(clk, 0x01);
204 	case nv_clk_src_hubk07:
205 		return read_clk(clk, 0x02);
206 	case nv_clk_src_hubk06:
207 		return read_clk(clk, 0x07);
208 	case nv_clk_src_hubk01:
209 		return read_clk(clk, 0x08);
210 	case nv_clk_src_daemon:
211 		return read_clk(clk, 0x0c);
212 	case nv_clk_src_vdec:
213 		return read_clk(clk, 0x0e);
214 	default:
215 		nv_error(clk, "invalid clock source %d\n", src);
216 		return -EINVAL;
217 	}
218 }
219 
220 static u32
221 calc_div(struct gk104_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
222 {
223 	u32 div = min((ref * 2) / freq, (u32)65);
224 	if (div < 2)
225 		div = 2;
226 
227 	*ddiv = div - 2;
228 	return (ref * 2) / div;
229 }
230 
231 static u32
232 calc_src(struct gk104_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
233 {
234 	u32 sclk;
235 
236 	/* use one of the fixed frequencies if possible */
237 	*ddiv = 0x00000000;
238 	switch (freq) {
239 	case  27000:
240 	case 108000:
241 		*dsrc = 0x00000000;
242 		if (freq == 108000)
243 			*dsrc |= 0x00030000;
244 		return freq;
245 	case 100000:
246 		*dsrc = 0x00000002;
247 		return freq;
248 	default:
249 		*dsrc = 0x00000003;
250 		break;
251 	}
252 
253 	/* otherwise, calculate the closest divider */
254 	sclk = read_vco(clk, 0x137160 + (idx * 4));
255 	if (idx < 7)
256 		sclk = calc_div(clk, idx, sclk, freq, ddiv);
257 	return sclk;
258 }
259 
260 static u32
261 calc_pll(struct gk104_clk *clk, int idx, u32 freq, u32 *coef)
262 {
263 	struct nvkm_bios *bios = nvkm_bios(clk);
264 	struct nvbios_pll limits;
265 	int N, M, P, ret;
266 
267 	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
268 	if (ret)
269 		return 0;
270 
271 	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
272 	if (!limits.refclk)
273 		return 0;
274 
275 	ret = gt215_pll_calc(nv_subdev(clk), &limits, freq, &N, NULL, &M, &P);
276 	if (ret <= 0)
277 		return 0;
278 
279 	*coef = (P << 16) | (N << 8) | M;
280 	return ret;
281 }
282 
283 static int
284 calc_clk(struct gk104_clk *clk,
285 	 struct nvkm_cstate *cstate, int idx, int dom)
286 {
287 	struct gk104_clk_info *info = &clk->eng[idx];
288 	u32 freq = cstate->domain[dom];
289 	u32 src0, div0, div1D, div1P = 0;
290 	u32 clk0, clk1 = 0;
291 
292 	/* invalid clock domain */
293 	if (!freq)
294 		return 0;
295 
296 	/* first possible path, using only dividers */
297 	clk0 = calc_src(clk, idx, freq, &src0, &div0);
298 	clk0 = calc_div(clk, idx, clk0, freq, &div1D);
299 
300 	/* see if we can get any closer using PLLs */
301 	if (clk0 != freq && (0x0000ff87 & (1 << idx))) {
302 		if (idx <= 7)
303 			clk1 = calc_pll(clk, idx, freq, &info->coef);
304 		else
305 			clk1 = cstate->domain[nv_clk_src_hubk06];
306 		clk1 = calc_div(clk, idx, clk1, freq, &div1P);
307 	}
308 
309 	/* select the method which gets closest to target freq */
310 	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
311 		info->dsrc = src0;
312 		if (div0) {
313 			info->ddiv |= 0x80000000;
314 			info->ddiv |= div0;
315 		}
316 		if (div1D) {
317 			info->mdiv |= 0x80000000;
318 			info->mdiv |= div1D;
319 		}
320 		info->ssel = 0;
321 		info->freq = clk0;
322 	} else {
323 		if (div1P) {
324 			info->mdiv |= 0x80000000;
325 			info->mdiv |= div1P << 8;
326 		}
327 		info->ssel = (1 << idx);
328 		info->dsrc = 0x40000100;
329 		info->freq = clk1;
330 	}
331 
332 	return 0;
333 }
334 
335 static int
336 gk104_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
337 {
338 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
339 	int ret;
340 
341 	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
342 	    (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
343 	    (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
344 	    (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
345 	    (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
346 	    (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) ||
347 	    (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
348 		return ret;
349 
350 	return 0;
351 }
352 
353 static void
354 gk104_clk_prog_0(struct gk104_clk *clk, int idx)
355 {
356 	struct gk104_clk_info *info = &clk->eng[idx];
357 	struct nvkm_device *device = clk->base.subdev.device;
358 	if (!info->ssel) {
359 		nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x8000003f, info->ddiv);
360 		nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);
361 	}
362 }
363 
364 static void
365 gk104_clk_prog_1_0(struct gk104_clk *clk, int idx)
366 {
367 	struct nvkm_device *device = clk->base.subdev.device;
368 	nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
369 	nv_wait(clk, 0x137100, (1 << idx), 0x00000000);
370 }
371 
372 static void
373 gk104_clk_prog_1_1(struct gk104_clk *clk, int idx)
374 {
375 	struct nvkm_device *device = clk->base.subdev.device;
376 	nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000000);
377 }
378 
379 static void
380 gk104_clk_prog_2(struct gk104_clk *clk, int idx)
381 {
382 	struct gk104_clk_info *info = &clk->eng[idx];
383 	struct nvkm_device *device = clk->base.subdev.device;
384 	const u32 addr = 0x137000 + (idx * 0x20);
385 	nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
386 	nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
387 	if (info->coef) {
388 		nvkm_wr32(device, addr + 0x04, info->coef);
389 		nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
390 		nv_wait(clk, addr + 0x00, 0x00020000, 0x00020000);
391 		nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
392 	}
393 }
394 
395 static void
396 gk104_clk_prog_3(struct gk104_clk *clk, int idx)
397 {
398 	struct gk104_clk_info *info = &clk->eng[idx];
399 	struct nvkm_device *device = clk->base.subdev.device;
400 	if (info->ssel)
401 		nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv);
402 	else
403 		nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv);
404 }
405 
406 static void
407 gk104_clk_prog_4_0(struct gk104_clk *clk, int idx)
408 {
409 	struct gk104_clk_info *info = &clk->eng[idx];
410 	struct nvkm_device *device = clk->base.subdev.device;
411 	if (info->ssel) {
412 		nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
413 		nv_wait(clk, 0x137100, (1 << idx), info->ssel);
414 	}
415 }
416 
417 static void
418 gk104_clk_prog_4_1(struct gk104_clk *clk, int idx)
419 {
420 	struct gk104_clk_info *info = &clk->eng[idx];
421 	struct nvkm_device *device = clk->base.subdev.device;
422 	if (info->ssel) {
423 		nvkm_mask(device, 0x137160 + (idx * 0x04), 0x40000000, 0x40000000);
424 		nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000100);
425 	}
426 }
427 
428 static int
429 gk104_clk_prog(struct nvkm_clk *obj)
430 {
431 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
432 	struct {
433 		u32 mask;
434 		void (*exec)(struct gk104_clk *, int);
435 	} stage[] = {
436 		{ 0x007f, gk104_clk_prog_0   }, /* div programming */
437 		{ 0x007f, gk104_clk_prog_1_0 }, /* select div mode */
438 		{ 0xff80, gk104_clk_prog_1_1 },
439 		{ 0x00ff, gk104_clk_prog_2   }, /* (maybe) program pll */
440 		{ 0xff80, gk104_clk_prog_3   }, /* final divider */
441 		{ 0x007f, gk104_clk_prog_4_0 }, /* (maybe) select pll mode */
442 		{ 0xff80, gk104_clk_prog_4_1 },
443 	};
444 	int i, j;
445 
446 	for (i = 0; i < ARRAY_SIZE(stage); i++) {
447 		for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
448 			if (!(stage[i].mask & (1 << j)))
449 				continue;
450 			if (!clk->eng[j].freq)
451 				continue;
452 			stage[i].exec(clk, j);
453 		}
454 	}
455 
456 	return 0;
457 }
458 
459 static void
460 gk104_clk_tidy(struct nvkm_clk *obj)
461 {
462 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
463 	memset(clk->eng, 0x00, sizeof(clk->eng));
464 }
465 
466 static struct nvkm_domain
467 gk104_domain[] = {
468 	{ nv_clk_src_crystal, 0xff },
469 	{ nv_clk_src_href   , 0xff },
470 	{ nv_clk_src_gpc    , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 },
471 	{ nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE },
472 	{ nv_clk_src_rop    , 0x02, NVKM_CLK_DOM_FLAG_CORE },
473 	{ nv_clk_src_mem    , 0x03, 0, "memory", 500 },
474 	{ nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE },
475 	{ nv_clk_src_hubk01 , 0x05 },
476 	{ nv_clk_src_vdec   , 0x06 },
477 	{ nv_clk_src_daemon , 0x07 },
478 	{ nv_clk_src_max }
479 };
480 
481 static int
482 gk104_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
483 	       struct nvkm_oclass *oclass, void *data, u32 size,
484 	       struct nvkm_object **pobject)
485 {
486 	struct gk104_clk *clk;
487 	int ret;
488 
489 	ret = nvkm_clk_create(parent, engine, oclass, gk104_domain,
490 			      NULL, 0, true, &clk);
491 	*pobject = nv_object(clk);
492 	if (ret)
493 		return ret;
494 
495 	clk->base.read = gk104_clk_read;
496 	clk->base.calc = gk104_clk_calc;
497 	clk->base.prog = gk104_clk_prog;
498 	clk->base.tidy = gk104_clk_tidy;
499 	return 0;
500 }
501 
502 struct nvkm_oclass
503 gk104_clk_oclass = {
504 	.handle = NV_SUBDEV(CLK, 0xe0),
505 	.ofuncs = &(struct nvkm_ofuncs) {
506 		.ctor = gk104_clk_ctor,
507 		.dtor = _nvkm_clk_dtor,
508 		.init = _nvkm_clk_init,
509 		.fini = _nvkm_clk_fini,
510 	},
511 };
512