1 /*
2  * Copyright 2013 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include <subdev/clk.h>
25 #include "pll.h"
26 
27 #include <subdev/timer.h>
28 #include <subdev/bios.h>
29 #include <subdev/bios/pll.h>
30 
31 struct gk104_clk_info {
32 	u32 freq;
33 	u32 ssel;
34 	u32 mdiv;
35 	u32 dsrc;
36 	u32 ddiv;
37 	u32 coef;
38 };
39 
40 struct gk104_clk {
41 	struct nvkm_clk base;
42 	struct gk104_clk_info eng[16];
43 };
44 
45 static u32 read_div(struct gk104_clk *, int, u32, u32);
46 static u32 read_pll(struct gk104_clk *, u32);
47 
48 static u32
49 read_vco(struct gk104_clk *clk, u32 dsrc)
50 {
51 	struct nvkm_device *device = clk->base.subdev.device;
52 	u32 ssrc = nvkm_rd32(device, dsrc);
53 	if (!(ssrc & 0x00000100))
54 		return read_pll(clk, 0x00e800);
55 	return read_pll(clk, 0x00e820);
56 }
57 
58 static u32
59 read_pll(struct gk104_clk *clk, u32 pll)
60 {
61 	struct nvkm_device *device = clk->base.subdev.device;
62 	u32 ctrl = nvkm_rd32(device, pll + 0x00);
63 	u32 coef = nvkm_rd32(device, pll + 0x04);
64 	u32 P = (coef & 0x003f0000) >> 16;
65 	u32 N = (coef & 0x0000ff00) >> 8;
66 	u32 M = (coef & 0x000000ff) >> 0;
67 	u32 sclk;
68 	u16 fN = 0xf000;
69 
70 	if (!(ctrl & 0x00000001))
71 		return 0;
72 
73 	switch (pll) {
74 	case 0x00e800:
75 	case 0x00e820:
76 		sclk = device->crystal;
77 		P = 1;
78 		break;
79 	case 0x132000:
80 		sclk = read_pll(clk, 0x132020);
81 		P = (coef & 0x10000000) ? 2 : 1;
82 		break;
83 	case 0x132020:
84 		sclk = read_div(clk, 0, 0x137320, 0x137330);
85 		fN   = nvkm_rd32(device, pll + 0x10) >> 16;
86 		break;
87 	case 0x137000:
88 	case 0x137020:
89 	case 0x137040:
90 	case 0x1370e0:
91 		sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
92 		break;
93 	default:
94 		return 0;
95 	}
96 
97 	if (P == 0)
98 		P = 1;
99 
100 	sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
101 	return sclk / (M * P);
102 }
103 
104 static u32
105 read_div(struct gk104_clk *clk, int doff, u32 dsrc, u32 dctl)
106 {
107 	struct nvkm_device *device = clk->base.subdev.device;
108 	u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
109 	u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
110 
111 	switch (ssrc & 0x00000003) {
112 	case 0:
113 		if ((ssrc & 0x00030000) != 0x00030000)
114 			return device->crystal;
115 		return 108000;
116 	case 2:
117 		return 100000;
118 	case 3:
119 		if (sctl & 0x80000000) {
120 			u32 sclk = read_vco(clk, dsrc + (doff * 4));
121 			u32 sdiv = (sctl & 0x0000003f) + 2;
122 			return (sclk * 2) / sdiv;
123 		}
124 
125 		return read_vco(clk, dsrc + (doff * 4));
126 	default:
127 		return 0;
128 	}
129 }
130 
131 static u32
132 read_mem(struct gk104_clk *clk)
133 {
134 	struct nvkm_device *device = clk->base.subdev.device;
135 	switch (nvkm_rd32(device, 0x1373f4) & 0x0000000f) {
136 	case 1: return read_pll(clk, 0x132020);
137 	case 2: return read_pll(clk, 0x132000);
138 	default:
139 		return 0;
140 	}
141 }
142 
143 static u32
144 read_clk(struct gk104_clk *clk, int idx)
145 {
146 	struct nvkm_device *device = clk->base.subdev.device;
147 	u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));
148 	u32 sclk, sdiv;
149 
150 	if (idx < 7) {
151 		u32 ssel = nvkm_rd32(device, 0x137100);
152 		if (ssel & (1 << idx)) {
153 			sclk = read_pll(clk, 0x137000 + (idx * 0x20));
154 			sdiv = 1;
155 		} else {
156 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
157 			sdiv = 0;
158 		}
159 	} else {
160 		u32 ssrc = nvkm_rd32(device, 0x137160 + (idx * 0x04));
161 		if ((ssrc & 0x00000003) == 0x00000003) {
162 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
163 			if (ssrc & 0x00000100) {
164 				if (ssrc & 0x40000000)
165 					sclk = read_pll(clk, 0x1370e0);
166 				sdiv = 1;
167 			} else {
168 				sdiv = 0;
169 			}
170 		} else {
171 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);
172 			sdiv = 0;
173 		}
174 	}
175 
176 	if (sctl & 0x80000000) {
177 		if (sdiv)
178 			sdiv = ((sctl & 0x00003f00) >> 8) + 2;
179 		else
180 			sdiv = ((sctl & 0x0000003f) >> 0) + 2;
181 		return (sclk * 2) / sdiv;
182 	}
183 
184 	return sclk;
185 }
186 
187 static int
188 gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
189 {
190 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
191 	struct nvkm_subdev *subdev = &clk->base.subdev;
192 	struct nvkm_device *device = subdev->device;
193 
194 	switch (src) {
195 	case nv_clk_src_crystal:
196 		return device->crystal;
197 	case nv_clk_src_href:
198 		return 100000;
199 	case nv_clk_src_mem:
200 		return read_mem(clk);
201 	case nv_clk_src_gpc:
202 		return read_clk(clk, 0x00);
203 	case nv_clk_src_rop:
204 		return read_clk(clk, 0x01);
205 	case nv_clk_src_hubk07:
206 		return read_clk(clk, 0x02);
207 	case nv_clk_src_hubk06:
208 		return read_clk(clk, 0x07);
209 	case nv_clk_src_hubk01:
210 		return read_clk(clk, 0x08);
211 	case nv_clk_src_daemon:
212 		return read_clk(clk, 0x0c);
213 	case nv_clk_src_vdec:
214 		return read_clk(clk, 0x0e);
215 	default:
216 		nvkm_error(subdev, "invalid clock source %d\n", src);
217 		return -EINVAL;
218 	}
219 }
220 
221 static u32
222 calc_div(struct gk104_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
223 {
224 	u32 div = min((ref * 2) / freq, (u32)65);
225 	if (div < 2)
226 		div = 2;
227 
228 	*ddiv = div - 2;
229 	return (ref * 2) / div;
230 }
231 
232 static u32
233 calc_src(struct gk104_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
234 {
235 	u32 sclk;
236 
237 	/* use one of the fixed frequencies if possible */
238 	*ddiv = 0x00000000;
239 	switch (freq) {
240 	case  27000:
241 	case 108000:
242 		*dsrc = 0x00000000;
243 		if (freq == 108000)
244 			*dsrc |= 0x00030000;
245 		return freq;
246 	case 100000:
247 		*dsrc = 0x00000002;
248 		return freq;
249 	default:
250 		*dsrc = 0x00000003;
251 		break;
252 	}
253 
254 	/* otherwise, calculate the closest divider */
255 	sclk = read_vco(clk, 0x137160 + (idx * 4));
256 	if (idx < 7)
257 		sclk = calc_div(clk, idx, sclk, freq, ddiv);
258 	return sclk;
259 }
260 
261 static u32
262 calc_pll(struct gk104_clk *clk, int idx, u32 freq, u32 *coef)
263 {
264 	struct nvkm_bios *bios = nvkm_bios(clk);
265 	struct nvbios_pll limits;
266 	int N, M, P, ret;
267 
268 	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
269 	if (ret)
270 		return 0;
271 
272 	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
273 	if (!limits.refclk)
274 		return 0;
275 
276 	ret = gt215_pll_calc(nv_subdev(clk), &limits, freq, &N, NULL, &M, &P);
277 	if (ret <= 0)
278 		return 0;
279 
280 	*coef = (P << 16) | (N << 8) | M;
281 	return ret;
282 }
283 
284 static int
285 calc_clk(struct gk104_clk *clk,
286 	 struct nvkm_cstate *cstate, int idx, int dom)
287 {
288 	struct gk104_clk_info *info = &clk->eng[idx];
289 	u32 freq = cstate->domain[dom];
290 	u32 src0, div0, div1D, div1P = 0;
291 	u32 clk0, clk1 = 0;
292 
293 	/* invalid clock domain */
294 	if (!freq)
295 		return 0;
296 
297 	/* first possible path, using only dividers */
298 	clk0 = calc_src(clk, idx, freq, &src0, &div0);
299 	clk0 = calc_div(clk, idx, clk0, freq, &div1D);
300 
301 	/* see if we can get any closer using PLLs */
302 	if (clk0 != freq && (0x0000ff87 & (1 << idx))) {
303 		if (idx <= 7)
304 			clk1 = calc_pll(clk, idx, freq, &info->coef);
305 		else
306 			clk1 = cstate->domain[nv_clk_src_hubk06];
307 		clk1 = calc_div(clk, idx, clk1, freq, &div1P);
308 	}
309 
310 	/* select the method which gets closest to target freq */
311 	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
312 		info->dsrc = src0;
313 		if (div0) {
314 			info->ddiv |= 0x80000000;
315 			info->ddiv |= div0;
316 		}
317 		if (div1D) {
318 			info->mdiv |= 0x80000000;
319 			info->mdiv |= div1D;
320 		}
321 		info->ssel = 0;
322 		info->freq = clk0;
323 	} else {
324 		if (div1P) {
325 			info->mdiv |= 0x80000000;
326 			info->mdiv |= div1P << 8;
327 		}
328 		info->ssel = (1 << idx);
329 		info->dsrc = 0x40000100;
330 		info->freq = clk1;
331 	}
332 
333 	return 0;
334 }
335 
336 static int
337 gk104_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
338 {
339 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
340 	int ret;
341 
342 	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
343 	    (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
344 	    (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
345 	    (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
346 	    (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
347 	    (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) ||
348 	    (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
349 		return ret;
350 
351 	return 0;
352 }
353 
354 static void
355 gk104_clk_prog_0(struct gk104_clk *clk, int idx)
356 {
357 	struct gk104_clk_info *info = &clk->eng[idx];
358 	struct nvkm_device *device = clk->base.subdev.device;
359 	if (!info->ssel) {
360 		nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x8000003f, info->ddiv);
361 		nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);
362 	}
363 }
364 
365 static void
366 gk104_clk_prog_1_0(struct gk104_clk *clk, int idx)
367 {
368 	struct nvkm_device *device = clk->base.subdev.device;
369 	nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
370 	nvkm_msec(device, 2000,
371 		if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
372 			break;
373 	);
374 }
375 
376 static void
377 gk104_clk_prog_1_1(struct gk104_clk *clk, int idx)
378 {
379 	struct nvkm_device *device = clk->base.subdev.device;
380 	nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000000);
381 }
382 
383 static void
384 gk104_clk_prog_2(struct gk104_clk *clk, int idx)
385 {
386 	struct gk104_clk_info *info = &clk->eng[idx];
387 	struct nvkm_device *device = clk->base.subdev.device;
388 	const u32 addr = 0x137000 + (idx * 0x20);
389 	nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
390 	nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
391 	if (info->coef) {
392 		nvkm_wr32(device, addr + 0x04, info->coef);
393 		nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
394 		nvkm_msec(device, 2000,
395 			if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
396 				break;
397 		);
398 		nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
399 	}
400 }
401 
402 static void
403 gk104_clk_prog_3(struct gk104_clk *clk, int idx)
404 {
405 	struct gk104_clk_info *info = &clk->eng[idx];
406 	struct nvkm_device *device = clk->base.subdev.device;
407 	if (info->ssel)
408 		nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv);
409 	else
410 		nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv);
411 }
412 
413 static void
414 gk104_clk_prog_4_0(struct gk104_clk *clk, int idx)
415 {
416 	struct gk104_clk_info *info = &clk->eng[idx];
417 	struct nvkm_device *device = clk->base.subdev.device;
418 	if (info->ssel) {
419 		nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
420 		nvkm_msec(device, 2000,
421 			u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
422 			if (tmp == info->ssel)
423 				break;
424 		);
425 	}
426 }
427 
428 static void
429 gk104_clk_prog_4_1(struct gk104_clk *clk, int idx)
430 {
431 	struct gk104_clk_info *info = &clk->eng[idx];
432 	struct nvkm_device *device = clk->base.subdev.device;
433 	if (info->ssel) {
434 		nvkm_mask(device, 0x137160 + (idx * 0x04), 0x40000000, 0x40000000);
435 		nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000100);
436 	}
437 }
438 
439 static int
440 gk104_clk_prog(struct nvkm_clk *obj)
441 {
442 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
443 	struct {
444 		u32 mask;
445 		void (*exec)(struct gk104_clk *, int);
446 	} stage[] = {
447 		{ 0x007f, gk104_clk_prog_0   }, /* div programming */
448 		{ 0x007f, gk104_clk_prog_1_0 }, /* select div mode */
449 		{ 0xff80, gk104_clk_prog_1_1 },
450 		{ 0x00ff, gk104_clk_prog_2   }, /* (maybe) program pll */
451 		{ 0xff80, gk104_clk_prog_3   }, /* final divider */
452 		{ 0x007f, gk104_clk_prog_4_0 }, /* (maybe) select pll mode */
453 		{ 0xff80, gk104_clk_prog_4_1 },
454 	};
455 	int i, j;
456 
457 	for (i = 0; i < ARRAY_SIZE(stage); i++) {
458 		for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
459 			if (!(stage[i].mask & (1 << j)))
460 				continue;
461 			if (!clk->eng[j].freq)
462 				continue;
463 			stage[i].exec(clk, j);
464 		}
465 	}
466 
467 	return 0;
468 }
469 
470 static void
471 gk104_clk_tidy(struct nvkm_clk *obj)
472 {
473 	struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
474 	memset(clk->eng, 0x00, sizeof(clk->eng));
475 }
476 
477 static struct nvkm_domain
478 gk104_domain[] = {
479 	{ nv_clk_src_crystal, 0xff },
480 	{ nv_clk_src_href   , 0xff },
481 	{ nv_clk_src_gpc    , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 },
482 	{ nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE },
483 	{ nv_clk_src_rop    , 0x02, NVKM_CLK_DOM_FLAG_CORE },
484 	{ nv_clk_src_mem    , 0x03, 0, "memory", 500 },
485 	{ nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE },
486 	{ nv_clk_src_hubk01 , 0x05 },
487 	{ nv_clk_src_vdec   , 0x06 },
488 	{ nv_clk_src_daemon , 0x07 },
489 	{ nv_clk_src_max }
490 };
491 
492 static int
493 gk104_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
494 	       struct nvkm_oclass *oclass, void *data, u32 size,
495 	       struct nvkm_object **pobject)
496 {
497 	struct gk104_clk *clk;
498 	int ret;
499 
500 	ret = nvkm_clk_create(parent, engine, oclass, gk104_domain,
501 			      NULL, 0, true, &clk);
502 	*pobject = nv_object(clk);
503 	if (ret)
504 		return ret;
505 
506 	clk->base.read = gk104_clk_read;
507 	clk->base.calc = gk104_clk_calc;
508 	clk->base.prog = gk104_clk_prog;
509 	clk->base.tidy = gk104_clk_tidy;
510 	return 0;
511 }
512 
513 struct nvkm_oclass
514 gk104_clk_oclass = {
515 	.handle = NV_SUBDEV(CLK, 0xe0),
516 	.ofuncs = &(struct nvkm_ofuncs) {
517 		.ctor = gk104_clk_ctor,
518 		.dtor = _nvkm_clk_dtor,
519 		.init = _nvkm_clk_init,
520 		.fini = _nvkm_clk_fini,
521 	},
522 };
523