1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include <subdev/clk.h>
25 #include "pll.h"
26 
27 #include <subdev/bios.h>
28 #include <subdev/bios/pll.h>
29 #include <subdev/timer.h>
30 
31 struct gf100_clk_info {
32 	u32 freq;
33 	u32 ssel;
34 	u32 mdiv;
35 	u32 dsrc;
36 	u32 ddiv;
37 	u32 coef;
38 };
39 
40 struct gf100_clk {
41 	struct nvkm_clk base;
42 	struct gf100_clk_info eng[16];
43 };
44 
45 static u32 read_div(struct gf100_clk *, int, u32, u32);
46 
47 static u32
48 read_vco(struct gf100_clk *clk, u32 dsrc)
49 {
50 	struct nvkm_device *device = clk->base.subdev.device;
51 	u32 ssrc = nvkm_rd32(device, dsrc);
52 	if (!(ssrc & 0x00000100))
53 		return clk->base.read(&clk->base, nv_clk_src_sppll0);
54 	return clk->base.read(&clk->base, nv_clk_src_sppll1);
55 }
56 
57 static u32
58 read_pll(struct gf100_clk *clk, u32 pll)
59 {
60 	struct nvkm_device *device = clk->base.subdev.device;
61 	u32 ctrl = nvkm_rd32(device, pll + 0x00);
62 	u32 coef = nvkm_rd32(device, pll + 0x04);
63 	u32 P = (coef & 0x003f0000) >> 16;
64 	u32 N = (coef & 0x0000ff00) >> 8;
65 	u32 M = (coef & 0x000000ff) >> 0;
66 	u32 sclk;
67 
68 	if (!(ctrl & 0x00000001))
69 		return 0;
70 
71 	switch (pll) {
72 	case 0x00e800:
73 	case 0x00e820:
74 		sclk = device->crystal;
75 		P = 1;
76 		break;
77 	case 0x132000:
78 		sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrc);
79 		break;
80 	case 0x132020:
81 		sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrcref);
82 		break;
83 	case 0x137000:
84 	case 0x137020:
85 	case 0x137040:
86 	case 0x1370e0:
87 		sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
88 		break;
89 	default:
90 		return 0;
91 	}
92 
93 	return sclk * N / M / P;
94 }
95 
96 static u32
97 read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
98 {
99 	struct nvkm_device *device = clk->base.subdev.device;
100 	u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
101 	u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
102 
103 	switch (ssrc & 0x00000003) {
104 	case 0:
105 		if ((ssrc & 0x00030000) != 0x00030000)
106 			return device->crystal;
107 		return 108000;
108 	case 2:
109 		return 100000;
110 	case 3:
111 		if (sctl & 0x80000000) {
112 			u32 sclk = read_vco(clk, dsrc + (doff * 4));
113 			u32 sdiv = (sctl & 0x0000003f) + 2;
114 			return (sclk * 2) / sdiv;
115 		}
116 
117 		return read_vco(clk, dsrc + (doff * 4));
118 	default:
119 		return 0;
120 	}
121 }
122 
123 static u32
124 read_clk(struct gf100_clk *clk, int idx)
125 {
126 	struct nvkm_device *device = clk->base.subdev.device;
127 	u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));
128 	u32 ssel = nvkm_rd32(device, 0x137100);
129 	u32 sclk, sdiv;
130 
131 	if (ssel & (1 << idx)) {
132 		if (idx < 7)
133 			sclk = read_pll(clk, 0x137000 + (idx * 0x20));
134 		else
135 			sclk = read_pll(clk, 0x1370e0);
136 		sdiv = ((sctl & 0x00003f00) >> 8) + 2;
137 	} else {
138 		sclk = read_div(clk, idx, 0x137160, 0x1371d0);
139 		sdiv = ((sctl & 0x0000003f) >> 0) + 2;
140 	}
141 
142 	if (sctl & 0x80000000)
143 		return (sclk * 2) / sdiv;
144 
145 	return sclk;
146 }
147 
148 static int
149 gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
150 {
151 	struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
152 	struct nvkm_subdev *subdev = &clk->base.subdev;
153 	struct nvkm_device *device = subdev->device;
154 
155 	switch (src) {
156 	case nv_clk_src_crystal:
157 		return device->crystal;
158 	case nv_clk_src_href:
159 		return 100000;
160 	case nv_clk_src_sppll0:
161 		return read_pll(clk, 0x00e800);
162 	case nv_clk_src_sppll1:
163 		return read_pll(clk, 0x00e820);
164 
165 	case nv_clk_src_mpllsrcref:
166 		return read_div(clk, 0, 0x137320, 0x137330);
167 	case nv_clk_src_mpllsrc:
168 		return read_pll(clk, 0x132020);
169 	case nv_clk_src_mpll:
170 		return read_pll(clk, 0x132000);
171 	case nv_clk_src_mdiv:
172 		return read_div(clk, 0, 0x137300, 0x137310);
173 	case nv_clk_src_mem:
174 		if (nvkm_rd32(device, 0x1373f0) & 0x00000002)
175 			return clk->base.read(&clk->base, nv_clk_src_mpll);
176 		return clk->base.read(&clk->base, nv_clk_src_mdiv);
177 
178 	case nv_clk_src_gpc:
179 		return read_clk(clk, 0x00);
180 	case nv_clk_src_rop:
181 		return read_clk(clk, 0x01);
182 	case nv_clk_src_hubk07:
183 		return read_clk(clk, 0x02);
184 	case nv_clk_src_hubk06:
185 		return read_clk(clk, 0x07);
186 	case nv_clk_src_hubk01:
187 		return read_clk(clk, 0x08);
188 	case nv_clk_src_copy:
189 		return read_clk(clk, 0x09);
190 	case nv_clk_src_daemon:
191 		return read_clk(clk, 0x0c);
192 	case nv_clk_src_vdec:
193 		return read_clk(clk, 0x0e);
194 	default:
195 		nvkm_error(subdev, "invalid clock source %d\n", src);
196 		return -EINVAL;
197 	}
198 }
199 
200 static u32
201 calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
202 {
203 	u32 div = min((ref * 2) / freq, (u32)65);
204 	if (div < 2)
205 		div = 2;
206 
207 	*ddiv = div - 2;
208 	return (ref * 2) / div;
209 }
210 
211 static u32
212 calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
213 {
214 	u32 sclk;
215 
216 	/* use one of the fixed frequencies if possible */
217 	*ddiv = 0x00000000;
218 	switch (freq) {
219 	case  27000:
220 	case 108000:
221 		*dsrc = 0x00000000;
222 		if (freq == 108000)
223 			*dsrc |= 0x00030000;
224 		return freq;
225 	case 100000:
226 		*dsrc = 0x00000002;
227 		return freq;
228 	default:
229 		*dsrc = 0x00000003;
230 		break;
231 	}
232 
233 	/* otherwise, calculate the closest divider */
234 	sclk = read_vco(clk, 0x137160 + (idx * 4));
235 	if (idx < 7)
236 		sclk = calc_div(clk, idx, sclk, freq, ddiv);
237 	return sclk;
238 }
239 
240 static u32
241 calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef)
242 {
243 	struct nvkm_bios *bios = nvkm_bios(clk);
244 	struct nvbios_pll limits;
245 	int N, M, P, ret;
246 
247 	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
248 	if (ret)
249 		return 0;
250 
251 	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
252 	if (!limits.refclk)
253 		return 0;
254 
255 	ret = gt215_pll_calc(nv_subdev(clk), &limits, freq, &N, NULL, &M, &P);
256 	if (ret <= 0)
257 		return 0;
258 
259 	*coef = (P << 16) | (N << 8) | M;
260 	return ret;
261 }
262 
263 static int
264 calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom)
265 {
266 	struct gf100_clk_info *info = &clk->eng[idx];
267 	u32 freq = cstate->domain[dom];
268 	u32 src0, div0, div1D, div1P = 0;
269 	u32 clk0, clk1 = 0;
270 
271 	/* invalid clock domain */
272 	if (!freq)
273 		return 0;
274 
275 	/* first possible path, using only dividers */
276 	clk0 = calc_src(clk, idx, freq, &src0, &div0);
277 	clk0 = calc_div(clk, idx, clk0, freq, &div1D);
278 
279 	/* see if we can get any closer using PLLs */
280 	if (clk0 != freq && (0x00004387 & (1 << idx))) {
281 		if (idx <= 7)
282 			clk1 = calc_pll(clk, idx, freq, &info->coef);
283 		else
284 			clk1 = cstate->domain[nv_clk_src_hubk06];
285 		clk1 = calc_div(clk, idx, clk1, freq, &div1P);
286 	}
287 
288 	/* select the method which gets closest to target freq */
289 	if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
290 		info->dsrc = src0;
291 		if (div0) {
292 			info->ddiv |= 0x80000000;
293 			info->ddiv |= div0 << 8;
294 			info->ddiv |= div0;
295 		}
296 		if (div1D) {
297 			info->mdiv |= 0x80000000;
298 			info->mdiv |= div1D;
299 		}
300 		info->ssel = info->coef = 0;
301 		info->freq = clk0;
302 	} else {
303 		if (div1P) {
304 			info->mdiv |= 0x80000000;
305 			info->mdiv |= div1P << 8;
306 		}
307 		info->ssel = (1 << idx);
308 		info->freq = clk1;
309 	}
310 
311 	return 0;
312 }
313 
314 static int
315 gf100_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
316 {
317 	struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
318 	int ret;
319 
320 	if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
321 	    (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
322 	    (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
323 	    (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
324 	    (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
325 	    (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) ||
326 	    (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) ||
327 	    (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
328 		return ret;
329 
330 	return 0;
331 }
332 
333 static void
334 gf100_clk_prog_0(struct gf100_clk *clk, int idx)
335 {
336 	struct gf100_clk_info *info = &clk->eng[idx];
337 	struct nvkm_device *device = clk->base.subdev.device;
338 	if (idx < 7 && !info->ssel) {
339 		nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv);
340 		nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);
341 	}
342 }
343 
344 static void
345 gf100_clk_prog_1(struct gf100_clk *clk, int idx)
346 {
347 	struct nvkm_device *device = clk->base.subdev.device;
348 	nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
349 	nvkm_msec(device, 2000,
350 		if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
351 			break;
352 	);
353 }
354 
355 static void
356 gf100_clk_prog_2(struct gf100_clk *clk, int idx)
357 {
358 	struct gf100_clk_info *info = &clk->eng[idx];
359 	struct nvkm_device *device = clk->base.subdev.device;
360 	const u32 addr = 0x137000 + (idx * 0x20);
361 	if (idx <= 7) {
362 		nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
363 		nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
364 		if (info->coef) {
365 			nvkm_wr32(device, addr + 0x04, info->coef);
366 			nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
367 			nvkm_msec(device, 2000,
368 				if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
369 					break;
370 			);
371 			nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
372 		}
373 	}
374 }
375 
376 static void
377 gf100_clk_prog_3(struct gf100_clk *clk, int idx)
378 {
379 	struct gf100_clk_info *info = &clk->eng[idx];
380 	struct nvkm_device *device = clk->base.subdev.device;
381 	if (info->ssel) {
382 		nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
383 		nvkm_msec(device, 2000,
384 			u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
385 			if (tmp == info->ssel)
386 				break;
387 		);
388 	}
389 }
390 
391 static void
392 gf100_clk_prog_4(struct gf100_clk *clk, int idx)
393 {
394 	struct gf100_clk_info *info = &clk->eng[idx];
395 	struct nvkm_device *device = clk->base.subdev.device;
396 	nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv);
397 }
398 
399 static int
400 gf100_clk_prog(struct nvkm_clk *obj)
401 {
402 	struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
403 	struct {
404 		void (*exec)(struct gf100_clk *, int);
405 	} stage[] = {
406 		{ gf100_clk_prog_0 }, /* div programming */
407 		{ gf100_clk_prog_1 }, /* select div mode */
408 		{ gf100_clk_prog_2 }, /* (maybe) program pll */
409 		{ gf100_clk_prog_3 }, /* (maybe) select pll mode */
410 		{ gf100_clk_prog_4 }, /* final divider */
411 	};
412 	int i, j;
413 
414 	for (i = 0; i < ARRAY_SIZE(stage); i++) {
415 		for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
416 			if (!clk->eng[j].freq)
417 				continue;
418 			stage[i].exec(clk, j);
419 		}
420 	}
421 
422 	return 0;
423 }
424 
425 static void
426 gf100_clk_tidy(struct nvkm_clk *obj)
427 {
428 	struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
429 	memset(clk->eng, 0x00, sizeof(clk->eng));
430 }
431 
432 static struct nvkm_domain
433 gf100_domain[] = {
434 	{ nv_clk_src_crystal, 0xff },
435 	{ nv_clk_src_href   , 0xff },
436 	{ nv_clk_src_hubk06 , 0x00 },
437 	{ nv_clk_src_hubk01 , 0x01 },
438 	{ nv_clk_src_copy   , 0x02 },
439 	{ nv_clk_src_gpc    , 0x03, 0, "core", 2000 },
440 	{ nv_clk_src_rop    , 0x04 },
441 	{ nv_clk_src_mem    , 0x05, 0, "memory", 1000 },
442 	{ nv_clk_src_vdec   , 0x06 },
443 	{ nv_clk_src_daemon , 0x0a },
444 	{ nv_clk_src_hubk07 , 0x0b },
445 	{ nv_clk_src_max }
446 };
447 
448 static int
449 gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
450 	       struct nvkm_oclass *oclass, void *data, u32 size,
451 	       struct nvkm_object **pobject)
452 {
453 	struct gf100_clk *clk;
454 	int ret;
455 
456 	ret = nvkm_clk_create(parent, engine, oclass, gf100_domain,
457 			      NULL, 0, false, &clk);
458 	*pobject = nv_object(clk);
459 	if (ret)
460 		return ret;
461 
462 	clk->base.read = gf100_clk_read;
463 	clk->base.calc = gf100_clk_calc;
464 	clk->base.prog = gf100_clk_prog;
465 	clk->base.tidy = gf100_clk_tidy;
466 	return 0;
467 }
468 
469 struct nvkm_oclass
470 gf100_clk_oclass = {
471 	.handle = NV_SUBDEV(CLK, 0xc0),
472 	.ofuncs = &(struct nvkm_ofuncs) {
473 		.ctor = gf100_clk_ctor,
474 		.dtor = _nvkm_clk_dtor,
475 		.init = _nvkm_clk_init,
476 		.fini = _nvkm_clk_fini,
477 	},
478 };
479