1 /*
2  * Copyright 2012 Nouveau Community
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Martin Peres <martin.peres@labri.fr>
23  *          Ben Skeggs
24  */
25 #include "nv04.h"
26 
27 #include <subdev/timer.h>
28 
29 static int
30 nv50_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size)
31 {
32 	int i;
33 
34 	nv_mask(bus, 0x001098, 0x00000008, 0x00000000);
35 	nv_wr32(bus, 0x001304, 0x00000000);
36 	for (i = 0; i < size; i++)
37 		nv_wr32(bus, 0x001400 + (i * 4), data[i]);
38 	nv_mask(bus, 0x001098, 0x00000018, 0x00000018);
39 	nv_wr32(bus, 0x00130c, 0x00000003);
40 
41 	return nv_wait(bus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
42 }
43 
44 void
45 nv50_bus_intr(struct nvkm_subdev *subdev)
46 {
47 	struct nvkm_bus *bus = nvkm_bus(subdev);
48 	u32 stat = nv_rd32(bus, 0x001100) & nv_rd32(bus, 0x001140);
49 
50 	if (stat & 0x00000008) {
51 		u32 addr = nv_rd32(bus, 0x009084);
52 		u32 data = nv_rd32(bus, 0x009088);
53 
54 		nv_error(bus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
55 			 (addr & 0x00000002) ? "write" : "read", data,
56 			 (addr & 0x00fffffc));
57 
58 		stat &= ~0x00000008;
59 		nv_wr32(bus, 0x001100, 0x00000008);
60 	}
61 
62 	if (stat & 0x00010000) {
63 		subdev = nvkm_subdev(bus, NVDEV_SUBDEV_THERM);
64 		if (subdev && subdev->intr)
65 			subdev->intr(subdev);
66 		stat &= ~0x00010000;
67 		nv_wr32(bus, 0x001100, 0x00010000);
68 	}
69 
70 	if (stat) {
71 		nv_error(bus, "unknown intr 0x%08x\n", stat);
72 		nv_mask(bus, 0x001140, stat, 0);
73 	}
74 }
75 
76 int
77 nv50_bus_init(struct nvkm_object *object)
78 {
79 	struct nvkm_bus *bus = (void *)object;
80 	int ret;
81 
82 	ret = nvkm_bus_init(bus);
83 	if (ret)
84 		return ret;
85 
86 	nv_wr32(bus, 0x001100, 0xffffffff);
87 	nv_wr32(bus, 0x001140, 0x00010008);
88 	return 0;
89 }
90 
91 struct nvkm_oclass *
92 nv50_bus_oclass = &(struct nv04_bus_impl) {
93 	.base.handle = NV_SUBDEV(BUS, 0x50),
94 	.base.ofuncs = &(struct nvkm_ofuncs) {
95 		.ctor = nv04_bus_ctor,
96 		.dtor = _nvkm_bus_dtor,
97 		.init = nv50_bus_init,
98 		.fini = _nvkm_bus_fini,
99 	},
100 	.intr = nv50_bus_intr,
101 	.hwsq_exec = nv50_bus_hwsq_exec,
102 	.hwsq_size = 64,
103 }.base;
104