1 /* 2 * Copyright 2012 Nouveau Community 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Martin Peres <martin.peres@labri.fr> 23 * Ben Skeggs 24 */ 25 #include "nv04.h" 26 27 #include <subdev/timer.h> 28 29 static int 30 nv50_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size) 31 { 32 struct nvkm_device *device = bus->subdev.device; 33 int i; 34 35 nvkm_mask(device, 0x001098, 0x00000008, 0x00000000); 36 nvkm_wr32(device, 0x001304, 0x00000000); 37 for (i = 0; i < size; i++) 38 nvkm_wr32(device, 0x001400 + (i * 4), data[i]); 39 nvkm_mask(device, 0x001098, 0x00000018, 0x00000018); 40 nvkm_wr32(device, 0x00130c, 0x00000003); 41 42 return nv_wait(bus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT; 43 } 44 45 void 46 nv50_bus_intr(struct nvkm_subdev *subdev) 47 { 48 struct nvkm_bus *bus = nvkm_bus(subdev); 49 struct nvkm_device *device = bus->subdev.device; 50 u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140); 51 52 if (stat & 0x00000008) { 53 u32 addr = nvkm_rd32(device, 0x009084); 54 u32 data = nvkm_rd32(device, 0x009088); 55 56 nv_error(bus, "MMIO %s of 0x%08x FAULT at 0x%06x\n", 57 (addr & 0x00000002) ? "write" : "read", data, 58 (addr & 0x00fffffc)); 59 60 stat &= ~0x00000008; 61 nvkm_wr32(device, 0x001100, 0x00000008); 62 } 63 64 if (stat & 0x00010000) { 65 subdev = nvkm_subdev(bus, NVDEV_SUBDEV_THERM); 66 if (subdev && subdev->intr) 67 subdev->intr(subdev); 68 stat &= ~0x00010000; 69 nvkm_wr32(device, 0x001100, 0x00010000); 70 } 71 72 if (stat) { 73 nv_error(bus, "unknown intr 0x%08x\n", stat); 74 nvkm_mask(device, 0x001140, stat, 0); 75 } 76 } 77 78 int 79 nv50_bus_init(struct nvkm_object *object) 80 { 81 struct nvkm_bus *bus = (void *)object; 82 struct nvkm_device *device = bus->subdev.device; 83 int ret; 84 85 ret = nvkm_bus_init(bus); 86 if (ret) 87 return ret; 88 89 nvkm_wr32(device, 0x001100, 0xffffffff); 90 nvkm_wr32(device, 0x001140, 0x00010008); 91 return 0; 92 } 93 94 struct nvkm_oclass * 95 nv50_bus_oclass = &(struct nv04_bus_impl) { 96 .base.handle = NV_SUBDEV(BUS, 0x50), 97 .base.ofuncs = &(struct nvkm_ofuncs) { 98 .ctor = nv04_bus_ctor, 99 .dtor = _nvkm_bus_dtor, 100 .init = nv50_bus_init, 101 .fini = _nvkm_bus_fini, 102 }, 103 .intr = nv50_bus_intr, 104 .hwsq_exec = nv50_bus_hwsq_exec, 105 .hwsq_size = 64, 106 }.base; 107