1 /* 2 * Copyright 2012 Nouveau Community 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Martin Peres <martin.peres@labri.fr> 23 * Ben Skeggs 24 */ 25 #include "nv04.h" 26 27 #include <subdev/therm.h> 28 #include <subdev/timer.h> 29 30 static int 31 nv50_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size) 32 { 33 struct nvkm_device *device = bus->subdev.device; 34 int i; 35 36 nvkm_mask(device, 0x001098, 0x00000008, 0x00000000); 37 nvkm_wr32(device, 0x001304, 0x00000000); 38 for (i = 0; i < size; i++) 39 nvkm_wr32(device, 0x001400 + (i * 4), data[i]); 40 nvkm_mask(device, 0x001098, 0x00000018, 0x00000018); 41 nvkm_wr32(device, 0x00130c, 0x00000003); 42 43 if (nvkm_msec(device, 2000, 44 if (!(nvkm_rd32(device, 0x001308) & 0x00000100)) 45 break; 46 ) < 0) 47 return -ETIMEDOUT; 48 49 return 0; 50 } 51 52 void 53 nv50_bus_intr(struct nvkm_subdev *subdev) 54 { 55 struct nvkm_device *device = subdev->device; 56 u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140); 57 58 if (stat & 0x00000008) { 59 u32 addr = nvkm_rd32(device, 0x009084); 60 u32 data = nvkm_rd32(device, 0x009088); 61 62 nvkm_error(subdev, "MMIO %s of %08x FAULT at %06x\n", 63 (addr & 0x00000002) ? "write" : "read", data, 64 (addr & 0x00fffffc)); 65 66 stat &= ~0x00000008; 67 nvkm_wr32(device, 0x001100, 0x00000008); 68 } 69 70 if (stat & 0x00010000) { 71 struct nvkm_therm *therm = device->therm; 72 if (therm) 73 nvkm_subdev_intr(&therm->subdev); 74 stat &= ~0x00010000; 75 nvkm_wr32(device, 0x001100, 0x00010000); 76 } 77 78 if (stat) { 79 nvkm_error(subdev, "intr %08x\n", stat); 80 nvkm_mask(device, 0x001140, stat, 0); 81 } 82 } 83 84 int 85 nv50_bus_init(struct nvkm_object *object) 86 { 87 struct nvkm_bus *bus = (void *)object; 88 struct nvkm_device *device = bus->subdev.device; 89 int ret; 90 91 ret = nvkm_bus_init(bus); 92 if (ret) 93 return ret; 94 95 nvkm_wr32(device, 0x001100, 0xffffffff); 96 nvkm_wr32(device, 0x001140, 0x00010008); 97 return 0; 98 } 99 100 struct nvkm_oclass * 101 nv50_bus_oclass = &(struct nv04_bus_impl) { 102 .base.handle = NV_SUBDEV(BUS, 0x50), 103 .base.ofuncs = &(struct nvkm_ofuncs) { 104 .ctor = nv04_bus_ctor, 105 .dtor = _nvkm_bus_dtor, 106 .init = nv50_bus_init, 107 .fini = _nvkm_bus_fini, 108 }, 109 .intr = nv50_bus_intr, 110 .hwsq_exec = nv50_bus_hwsq_exec, 111 .hwsq_size = 64, 112 }.base; 113