1 /* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #include <subdev/bios.h> 25 #include <subdev/bios/bit.h> 26 #include <subdev/bios/bmp.h> 27 #include <subdev/bios/pll.h> 28 #include <subdev/vga.h> 29 30 31 struct pll_mapping { 32 u8 type; 33 u32 reg; 34 }; 35 36 static struct pll_mapping 37 nv04_pll_mapping[] = { 38 { PLL_CORE , 0x680500 }, 39 { PLL_MEMORY, 0x680504 }, 40 { PLL_VPLL0 , 0x680508 }, 41 { PLL_VPLL1 , 0x680520 }, 42 {} 43 }; 44 45 static struct pll_mapping 46 nv40_pll_mapping[] = { 47 { PLL_CORE , 0x004000 }, 48 { PLL_MEMORY, 0x004020 }, 49 { PLL_VPLL0 , 0x680508 }, 50 { PLL_VPLL1 , 0x680520 }, 51 {} 52 }; 53 54 static struct pll_mapping 55 nv50_pll_mapping[] = { 56 { PLL_CORE , 0x004028 }, 57 { PLL_SHADER, 0x004020 }, 58 { PLL_UNK03 , 0x004000 }, 59 { PLL_MEMORY, 0x004008 }, 60 { PLL_UNK40 , 0x00e810 }, 61 { PLL_UNK41 , 0x00e818 }, 62 { PLL_UNK42 , 0x00e824 }, 63 { PLL_VPLL0 , 0x614100 }, 64 { PLL_VPLL1 , 0x614900 }, 65 {} 66 }; 67 68 static struct pll_mapping 69 g84_pll_mapping[] = { 70 { PLL_CORE , 0x004028 }, 71 { PLL_SHADER, 0x004020 }, 72 { PLL_MEMORY, 0x004008 }, 73 { PLL_VDEC , 0x004030 }, 74 { PLL_UNK41 , 0x00e818 }, 75 { PLL_VPLL0 , 0x614100 }, 76 { PLL_VPLL1 , 0x614900 }, 77 {} 78 }; 79 80 static u16 81 pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) 82 { 83 struct bit_entry bit_C; 84 85 if (!bit_entry(bios, 'C', &bit_C) && bit_C.length >= 10) { 86 u16 data = nv_ro16(bios, bit_C.offset + 8); 87 if (data) { 88 *ver = nv_ro08(bios, data + 0); 89 *hdr = nv_ro08(bios, data + 1); 90 *len = nv_ro08(bios, data + 2); 91 *cnt = nv_ro08(bios, data + 3); 92 return data; 93 } 94 } 95 96 if (bmp_version(bios) >= 0x0524) { 97 u16 data = nv_ro16(bios, bios->bmp_offset + 142); 98 if (data) { 99 *ver = nv_ro08(bios, data + 0); 100 *hdr = 1; 101 *cnt = 1; 102 *len = 0x18; 103 return data; 104 } 105 } 106 107 *ver = 0x00; 108 return 0x0000; 109 } 110 111 static struct pll_mapping * 112 pll_map(struct nvkm_bios *bios) 113 { 114 switch (nv_device(bios)->card_type) { 115 case NV_04: 116 case NV_10: 117 case NV_11: 118 case NV_20: 119 case NV_30: 120 return nv04_pll_mapping; 121 break; 122 case NV_40: 123 return nv40_pll_mapping; 124 case NV_50: 125 if (nv_device(bios)->chipset == 0x50) 126 return nv50_pll_mapping; 127 else 128 if (nv_device(bios)->chipset < 0xa3 || 129 nv_device(bios)->chipset == 0xaa || 130 nv_device(bios)->chipset == 0xac) 131 return g84_pll_mapping; 132 default: 133 return NULL; 134 } 135 } 136 137 static u16 138 pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) 139 { 140 struct pll_mapping *map; 141 u8 hdr, cnt; 142 u16 data; 143 144 data = pll_limits_table(bios, ver, &hdr, &cnt, len); 145 if (data && *ver >= 0x30) { 146 data += hdr; 147 while (cnt--) { 148 if (nv_ro32(bios, data + 3) == reg) { 149 *type = nv_ro08(bios, data + 0); 150 return data; 151 } 152 data += *len; 153 } 154 return 0x0000; 155 } 156 157 map = pll_map(bios); 158 while (map->reg) { 159 if (map->reg == reg && *ver >= 0x20) { 160 u16 addr = (data += hdr); 161 *type = map->type; 162 while (cnt--) { 163 if (nv_ro32(bios, data) == map->reg) 164 return data; 165 data += *len; 166 } 167 return addr; 168 } else 169 if (map->reg == reg) { 170 *type = map->type; 171 return data + 1; 172 } 173 map++; 174 } 175 176 return 0x0000; 177 } 178 179 static u16 180 pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) 181 { 182 struct pll_mapping *map; 183 u8 hdr, cnt; 184 u16 data; 185 186 data = pll_limits_table(bios, ver, &hdr, &cnt, len); 187 if (data && *ver >= 0x30) { 188 data += hdr; 189 while (cnt--) { 190 if (nv_ro08(bios, data + 0) == type) { 191 *reg = nv_ro32(bios, data + 3); 192 return data; 193 } 194 data += *len; 195 } 196 return 0x0000; 197 } 198 199 map = pll_map(bios); 200 while (map->reg) { 201 if (map->type == type && *ver >= 0x20) { 202 u16 addr = (data += hdr); 203 *reg = map->reg; 204 while (cnt--) { 205 if (nv_ro32(bios, data) == map->reg) 206 return data; 207 data += *len; 208 } 209 return addr; 210 } else 211 if (map->type == type) { 212 *reg = map->reg; 213 return data + 1; 214 } 215 map++; 216 } 217 218 return 0x0000; 219 } 220 221 int 222 nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info) 223 { 224 struct nvkm_subdev *subdev = &bios->subdev; 225 struct nvkm_device *device = subdev->device; 226 u8 ver, len; 227 u32 reg = type; 228 u16 data; 229 230 if (type > PLL_MAX) { 231 reg = type; 232 data = pll_map_reg(bios, reg, &type, &ver, &len); 233 } else { 234 data = pll_map_type(bios, type, ®, &ver, &len); 235 } 236 237 if (ver && !data) 238 return -ENOENT; 239 240 memset(info, 0, sizeof(*info)); 241 info->type = type; 242 info->reg = reg; 243 244 switch (ver) { 245 case 0x00: 246 break; 247 case 0x10: 248 case 0x11: 249 info->vco1.min_freq = nv_ro32(bios, data + 0); 250 info->vco1.max_freq = nv_ro32(bios, data + 4); 251 info->vco2.min_freq = nv_ro32(bios, data + 8); 252 info->vco2.max_freq = nv_ro32(bios, data + 12); 253 info->vco1.min_inputfreq = nv_ro32(bios, data + 16); 254 info->vco2.min_inputfreq = nv_ro32(bios, data + 20); 255 info->vco1.max_inputfreq = INT_MAX; 256 info->vco2.max_inputfreq = INT_MAX; 257 258 info->max_p = 0x7; 259 info->max_p_usable = 0x6; 260 261 /* these values taken from nv30/31/36 */ 262 switch (bios->version.chip) { 263 case 0x36: 264 info->vco1.min_n = 0x5; 265 break; 266 default: 267 info->vco1.min_n = 0x1; 268 break; 269 } 270 info->vco1.max_n = 0xff; 271 info->vco1.min_m = 0x1; 272 info->vco1.max_m = 0xd; 273 274 /* 275 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 276 * table version (apart from nv35)), N2 is compared to 277 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 278 * save a comparison 279 */ 280 info->vco2.min_n = 0x4; 281 switch (bios->version.chip) { 282 case 0x30: 283 case 0x35: 284 info->vco2.max_n = 0x1f; 285 break; 286 default: 287 info->vco2.max_n = 0x28; 288 break; 289 } 290 info->vco2.min_m = 0x1; 291 info->vco2.max_m = 0x4; 292 break; 293 case 0x20: 294 case 0x21: 295 info->vco1.min_freq = nv_ro16(bios, data + 4) * 1000; 296 info->vco1.max_freq = nv_ro16(bios, data + 6) * 1000; 297 info->vco2.min_freq = nv_ro16(bios, data + 8) * 1000; 298 info->vco2.max_freq = nv_ro16(bios, data + 10) * 1000; 299 info->vco1.min_inputfreq = nv_ro16(bios, data + 12) * 1000; 300 info->vco2.min_inputfreq = nv_ro16(bios, data + 14) * 1000; 301 info->vco1.max_inputfreq = nv_ro16(bios, data + 16) * 1000; 302 info->vco2.max_inputfreq = nv_ro16(bios, data + 18) * 1000; 303 info->vco1.min_n = nv_ro08(bios, data + 20); 304 info->vco1.max_n = nv_ro08(bios, data + 21); 305 info->vco1.min_m = nv_ro08(bios, data + 22); 306 info->vco1.max_m = nv_ro08(bios, data + 23); 307 info->vco2.min_n = nv_ro08(bios, data + 24); 308 info->vco2.max_n = nv_ro08(bios, data + 25); 309 info->vco2.min_m = nv_ro08(bios, data + 26); 310 info->vco2.max_m = nv_ro08(bios, data + 27); 311 312 info->max_p = nv_ro08(bios, data + 29); 313 info->max_p_usable = info->max_p; 314 if (bios->version.chip < 0x60) 315 info->max_p_usable = 0x6; 316 info->bias_p = nv_ro08(bios, data + 30); 317 318 if (len > 0x22) 319 info->refclk = nv_ro32(bios, data + 31); 320 break; 321 case 0x30: 322 data = nv_ro16(bios, data + 1); 323 324 info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000; 325 info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000; 326 info->vco2.min_freq = nv_ro16(bios, data + 4) * 1000; 327 info->vco2.max_freq = nv_ro16(bios, data + 6) * 1000; 328 info->vco1.min_inputfreq = nv_ro16(bios, data + 8) * 1000; 329 info->vco2.min_inputfreq = nv_ro16(bios, data + 10) * 1000; 330 info->vco1.max_inputfreq = nv_ro16(bios, data + 12) * 1000; 331 info->vco2.max_inputfreq = nv_ro16(bios, data + 14) * 1000; 332 info->vco1.min_n = nv_ro08(bios, data + 16); 333 info->vco1.max_n = nv_ro08(bios, data + 17); 334 info->vco1.min_m = nv_ro08(bios, data + 18); 335 info->vco1.max_m = nv_ro08(bios, data + 19); 336 info->vco2.min_n = nv_ro08(bios, data + 20); 337 info->vco2.max_n = nv_ro08(bios, data + 21); 338 info->vco2.min_m = nv_ro08(bios, data + 22); 339 info->vco2.max_m = nv_ro08(bios, data + 23); 340 info->max_p_usable = info->max_p = nv_ro08(bios, data + 25); 341 info->bias_p = nv_ro08(bios, data + 27); 342 info->refclk = nv_ro32(bios, data + 28); 343 break; 344 case 0x40: 345 info->refclk = nv_ro16(bios, data + 9) * 1000; 346 data = nv_ro16(bios, data + 1); 347 348 info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000; 349 info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000; 350 info->vco1.min_inputfreq = nv_ro16(bios, data + 4) * 1000; 351 info->vco1.max_inputfreq = nv_ro16(bios, data + 6) * 1000; 352 info->vco1.min_m = nv_ro08(bios, data + 8); 353 info->vco1.max_m = nv_ro08(bios, data + 9); 354 info->vco1.min_n = nv_ro08(bios, data + 10); 355 info->vco1.max_n = nv_ro08(bios, data + 11); 356 info->min_p = nv_ro08(bios, data + 12); 357 info->max_p = nv_ro08(bios, data + 13); 358 break; 359 default: 360 nvkm_error(subdev, "unknown pll limits version 0x%02x\n", ver); 361 return -EINVAL; 362 } 363 364 if (!info->refclk) { 365 info->refclk = device->crystal; 366 if (bios->version.chip == 0x51) { 367 u32 sel_clk = nvkm_rd32(device, 0x680524); 368 if ((info->reg == 0x680508 && sel_clk & 0x20) || 369 (info->reg == 0x680520 && sel_clk & 0x80)) { 370 if (nv_rdvgac(bios, 0, 0x27) < 0xa3) 371 info->refclk = 200000; 372 else 373 info->refclk = 25000; 374 } 375 } 376 } 377 378 /* 379 * By now any valid limit table ought to have set a max frequency for 380 * vco1, so if it's zero it's either a pre limit table bios, or one 381 * with an empty limit table (seen on nv18) 382 */ 383 if (!info->vco1.max_freq) { 384 info->vco1.max_freq = nv_ro32(bios, bios->bmp_offset + 67); 385 info->vco1.min_freq = nv_ro32(bios, bios->bmp_offset + 71); 386 if (bmp_version(bios) < 0x0506) { 387 info->vco1.max_freq = 256000; 388 info->vco1.min_freq = 128000; 389 } 390 391 info->vco1.min_inputfreq = 0; 392 info->vco1.max_inputfreq = INT_MAX; 393 info->vco1.min_n = 0x1; 394 info->vco1.max_n = 0xff; 395 info->vco1.min_m = 0x1; 396 397 if (device->crystal == 13500) { 398 /* nv05 does this, nv11 doesn't, nv10 unknown */ 399 if (bios->version.chip < 0x11) 400 info->vco1.min_m = 0x7; 401 info->vco1.max_m = 0xd; 402 } else { 403 if (bios->version.chip < 0x11) 404 info->vco1.min_m = 0x8; 405 info->vco1.max_m = 0xe; 406 } 407 408 if (bios->version.chip < 0x17 || 409 bios->version.chip == 0x1a || 410 bios->version.chip == 0x20) 411 info->max_p = 4; 412 else 413 info->max_p = 5; 414 info->max_p_usable = info->max_p; 415 } 416 417 return 0; 418 } 419