1 /* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #include <subdev/bios.h> 25 #include <subdev/bios/bit.h> 26 #include <subdev/bios/bmp.h> 27 #include <subdev/bios/pll.h> 28 #include <subdev/vga.h> 29 30 31 struct pll_mapping { 32 u8 type; 33 u32 reg; 34 }; 35 36 static struct pll_mapping 37 nv04_pll_mapping[] = { 38 { PLL_CORE , 0x680500 }, 39 { PLL_MEMORY, 0x680504 }, 40 { PLL_VPLL0 , 0x680508 }, 41 { PLL_VPLL1 , 0x680520 }, 42 {} 43 }; 44 45 static struct pll_mapping 46 nv40_pll_mapping[] = { 47 { PLL_CORE , 0x004000 }, 48 { PLL_MEMORY, 0x004020 }, 49 { PLL_VPLL0 , 0x680508 }, 50 { PLL_VPLL1 , 0x680520 }, 51 {} 52 }; 53 54 static struct pll_mapping 55 nv50_pll_mapping[] = { 56 { PLL_CORE , 0x004028 }, 57 { PLL_SHADER, 0x004020 }, 58 { PLL_UNK03 , 0x004000 }, 59 { PLL_MEMORY, 0x004008 }, 60 { PLL_UNK40 , 0x00e810 }, 61 { PLL_UNK41 , 0x00e818 }, 62 { PLL_UNK42 , 0x00e824 }, 63 { PLL_VPLL0 , 0x614100 }, 64 { PLL_VPLL1 , 0x614900 }, 65 {} 66 }; 67 68 static struct pll_mapping 69 g84_pll_mapping[] = { 70 { PLL_CORE , 0x004028 }, 71 { PLL_SHADER, 0x004020 }, 72 { PLL_MEMORY, 0x004008 }, 73 { PLL_VDEC , 0x004030 }, 74 { PLL_UNK41 , 0x00e818 }, 75 { PLL_VPLL0 , 0x614100 }, 76 { PLL_VPLL1 , 0x614900 }, 77 {} 78 }; 79 80 static u16 81 pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) 82 { 83 struct bit_entry bit_C; 84 85 if (!bit_entry(bios, 'C', &bit_C) && bit_C.length >= 10) { 86 u16 data = nvbios_rd16(bios, bit_C.offset + 8); 87 if (data) { 88 *ver = nvbios_rd08(bios, data + 0); 89 *hdr = nvbios_rd08(bios, data + 1); 90 *len = nvbios_rd08(bios, data + 2); 91 *cnt = nvbios_rd08(bios, data + 3); 92 return data; 93 } 94 } 95 96 if (bmp_version(bios) >= 0x0524) { 97 u16 data = nvbios_rd16(bios, bios->bmp_offset + 142); 98 if (data) { 99 *ver = nvbios_rd08(bios, data + 0); 100 *hdr = 1; 101 *cnt = 1; 102 *len = 0x18; 103 return data; 104 } 105 } 106 107 *ver = 0x00; 108 return 0x0000; 109 } 110 111 static struct pll_mapping * 112 pll_map(struct nvkm_bios *bios) 113 { 114 struct nvkm_device *device = bios->subdev.device; 115 switch (device->card_type) { 116 case NV_04: 117 case NV_10: 118 case NV_11: 119 case NV_20: 120 case NV_30: 121 return nv04_pll_mapping; 122 break; 123 case NV_40: 124 return nv40_pll_mapping; 125 case NV_50: 126 if (device->chipset == 0x50) 127 return nv50_pll_mapping; 128 else 129 if (device->chipset < 0xa3 || 130 device->chipset == 0xaa || 131 device->chipset == 0xac) 132 return g84_pll_mapping; 133 default: 134 return NULL; 135 } 136 } 137 138 static u16 139 pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) 140 { 141 struct pll_mapping *map; 142 u8 hdr, cnt; 143 u16 data; 144 145 data = pll_limits_table(bios, ver, &hdr, &cnt, len); 146 if (data && *ver >= 0x30) { 147 data += hdr; 148 while (cnt--) { 149 if (nvbios_rd32(bios, data + 3) == reg) { 150 *type = nvbios_rd08(bios, data + 0); 151 return data; 152 } 153 data += *len; 154 } 155 return 0x0000; 156 } 157 158 map = pll_map(bios); 159 while (map->reg) { 160 if (map->reg == reg && *ver >= 0x20) { 161 u16 addr = (data += hdr); 162 *type = map->type; 163 while (cnt--) { 164 if (nvbios_rd32(bios, data) == map->reg) 165 return data; 166 data += *len; 167 } 168 return addr; 169 } else 170 if (map->reg == reg) { 171 *type = map->type; 172 return data + 1; 173 } 174 map++; 175 } 176 177 return 0x0000; 178 } 179 180 static u16 181 pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) 182 { 183 struct pll_mapping *map; 184 u8 hdr, cnt; 185 u16 data; 186 187 data = pll_limits_table(bios, ver, &hdr, &cnt, len); 188 if (data && *ver >= 0x30) { 189 data += hdr; 190 while (cnt--) { 191 if (nvbios_rd08(bios, data + 0) == type) { 192 *reg = nvbios_rd32(bios, data + 3); 193 return data; 194 } 195 data += *len; 196 } 197 return 0x0000; 198 } 199 200 map = pll_map(bios); 201 while (map->reg) { 202 if (map->type == type && *ver >= 0x20) { 203 u16 addr = (data += hdr); 204 *reg = map->reg; 205 while (cnt--) { 206 if (nvbios_rd32(bios, data) == map->reg) 207 return data; 208 data += *len; 209 } 210 return addr; 211 } else 212 if (map->type == type) { 213 *reg = map->reg; 214 return data + 1; 215 } 216 map++; 217 } 218 219 return 0x0000; 220 } 221 222 int 223 nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info) 224 { 225 struct nvkm_subdev *subdev = &bios->subdev; 226 struct nvkm_device *device = subdev->device; 227 u8 ver, len; 228 u32 reg = type; 229 u16 data; 230 231 if (type > PLL_MAX) { 232 reg = type; 233 data = pll_map_reg(bios, reg, &type, &ver, &len); 234 } else { 235 data = pll_map_type(bios, type, ®, &ver, &len); 236 } 237 238 if (ver && !data) 239 return -ENOENT; 240 241 memset(info, 0, sizeof(*info)); 242 info->type = type; 243 info->reg = reg; 244 245 switch (ver) { 246 case 0x00: 247 break; 248 case 0x10: 249 case 0x11: 250 info->vco1.min_freq = nvbios_rd32(bios, data + 0); 251 info->vco1.max_freq = nvbios_rd32(bios, data + 4); 252 info->vco2.min_freq = nvbios_rd32(bios, data + 8); 253 info->vco2.max_freq = nvbios_rd32(bios, data + 12); 254 info->vco1.min_inputfreq = nvbios_rd32(bios, data + 16); 255 info->vco2.min_inputfreq = nvbios_rd32(bios, data + 20); 256 info->vco1.max_inputfreq = INT_MAX; 257 info->vco2.max_inputfreq = INT_MAX; 258 259 info->max_p = 0x7; 260 info->max_p_usable = 0x6; 261 262 /* these values taken from nv30/31/36 */ 263 switch (bios->version.chip) { 264 case 0x36: 265 info->vco1.min_n = 0x5; 266 break; 267 default: 268 info->vco1.min_n = 0x1; 269 break; 270 } 271 info->vco1.max_n = 0xff; 272 info->vco1.min_m = 0x1; 273 info->vco1.max_m = 0xd; 274 275 /* 276 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 277 * table version (apart from nv35)), N2 is compared to 278 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 279 * save a comparison 280 */ 281 info->vco2.min_n = 0x4; 282 switch (bios->version.chip) { 283 case 0x30: 284 case 0x35: 285 info->vco2.max_n = 0x1f; 286 break; 287 default: 288 info->vco2.max_n = 0x28; 289 break; 290 } 291 info->vco2.min_m = 0x1; 292 info->vco2.max_m = 0x4; 293 break; 294 case 0x20: 295 case 0x21: 296 info->vco1.min_freq = nvbios_rd16(bios, data + 4) * 1000; 297 info->vco1.max_freq = nvbios_rd16(bios, data + 6) * 1000; 298 info->vco2.min_freq = nvbios_rd16(bios, data + 8) * 1000; 299 info->vco2.max_freq = nvbios_rd16(bios, data + 10) * 1000; 300 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 12) * 1000; 301 info->vco2.min_inputfreq = nvbios_rd16(bios, data + 14) * 1000; 302 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 16) * 1000; 303 info->vco2.max_inputfreq = nvbios_rd16(bios, data + 18) * 1000; 304 info->vco1.min_n = nvbios_rd08(bios, data + 20); 305 info->vco1.max_n = nvbios_rd08(bios, data + 21); 306 info->vco1.min_m = nvbios_rd08(bios, data + 22); 307 info->vco1.max_m = nvbios_rd08(bios, data + 23); 308 info->vco2.min_n = nvbios_rd08(bios, data + 24); 309 info->vco2.max_n = nvbios_rd08(bios, data + 25); 310 info->vco2.min_m = nvbios_rd08(bios, data + 26); 311 info->vco2.max_m = nvbios_rd08(bios, data + 27); 312 313 info->max_p = nvbios_rd08(bios, data + 29); 314 info->max_p_usable = info->max_p; 315 if (bios->version.chip < 0x60) 316 info->max_p_usable = 0x6; 317 info->bias_p = nvbios_rd08(bios, data + 30); 318 319 if (len > 0x22) 320 info->refclk = nvbios_rd32(bios, data + 31); 321 break; 322 case 0x30: 323 data = nvbios_rd16(bios, data + 1); 324 325 info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000; 326 info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000; 327 info->vco2.min_freq = nvbios_rd16(bios, data + 4) * 1000; 328 info->vco2.max_freq = nvbios_rd16(bios, data + 6) * 1000; 329 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 8) * 1000; 330 info->vco2.min_inputfreq = nvbios_rd16(bios, data + 10) * 1000; 331 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 12) * 1000; 332 info->vco2.max_inputfreq = nvbios_rd16(bios, data + 14) * 1000; 333 info->vco1.min_n = nvbios_rd08(bios, data + 16); 334 info->vco1.max_n = nvbios_rd08(bios, data + 17); 335 info->vco1.min_m = nvbios_rd08(bios, data + 18); 336 info->vco1.max_m = nvbios_rd08(bios, data + 19); 337 info->vco2.min_n = nvbios_rd08(bios, data + 20); 338 info->vco2.max_n = nvbios_rd08(bios, data + 21); 339 info->vco2.min_m = nvbios_rd08(bios, data + 22); 340 info->vco2.max_m = nvbios_rd08(bios, data + 23); 341 info->max_p_usable = info->max_p = nvbios_rd08(bios, data + 25); 342 info->bias_p = nvbios_rd08(bios, data + 27); 343 info->refclk = nvbios_rd32(bios, data + 28); 344 break; 345 case 0x40: 346 info->refclk = nvbios_rd16(bios, data + 9) * 1000; 347 data = nvbios_rd16(bios, data + 1); 348 349 info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000; 350 info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000; 351 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 4) * 1000; 352 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 6) * 1000; 353 info->vco1.min_m = nvbios_rd08(bios, data + 8); 354 info->vco1.max_m = nvbios_rd08(bios, data + 9); 355 info->vco1.min_n = nvbios_rd08(bios, data + 10); 356 info->vco1.max_n = nvbios_rd08(bios, data + 11); 357 info->min_p = nvbios_rd08(bios, data + 12); 358 info->max_p = nvbios_rd08(bios, data + 13); 359 break; 360 default: 361 nvkm_error(subdev, "unknown pll limits version 0x%02x\n", ver); 362 return -EINVAL; 363 } 364 365 if (!info->refclk) { 366 info->refclk = device->crystal; 367 if (bios->version.chip == 0x51) { 368 u32 sel_clk = nvkm_rd32(device, 0x680524); 369 if ((info->reg == 0x680508 && sel_clk & 0x20) || 370 (info->reg == 0x680520 && sel_clk & 0x80)) { 371 if (nvkm_rdvgac(device, 0, 0x27) < 0xa3) 372 info->refclk = 200000; 373 else 374 info->refclk = 25000; 375 } 376 } 377 } 378 379 /* 380 * By now any valid limit table ought to have set a max frequency for 381 * vco1, so if it's zero it's either a pre limit table bios, or one 382 * with an empty limit table (seen on nv18) 383 */ 384 if (!info->vco1.max_freq) { 385 info->vco1.max_freq = nvbios_rd32(bios, bios->bmp_offset + 67); 386 info->vco1.min_freq = nvbios_rd32(bios, bios->bmp_offset + 71); 387 if (bmp_version(bios) < 0x0506) { 388 info->vco1.max_freq = 256000; 389 info->vco1.min_freq = 128000; 390 } 391 392 info->vco1.min_inputfreq = 0; 393 info->vco1.max_inputfreq = INT_MAX; 394 info->vco1.min_n = 0x1; 395 info->vco1.max_n = 0xff; 396 info->vco1.min_m = 0x1; 397 398 if (device->crystal == 13500) { 399 /* nv05 does this, nv11 doesn't, nv10 unknown */ 400 if (bios->version.chip < 0x11) 401 info->vco1.min_m = 0x7; 402 info->vco1.max_m = 0xd; 403 } else { 404 if (bios->version.chip < 0x11) 405 info->vco1.min_m = 0x8; 406 info->vco1.max_m = 0xe; 407 } 408 409 if (bios->version.chip < 0x17 || 410 bios->version.chip == 0x1a || 411 bios->version.chip == 0x20) 412 info->max_p = 4; 413 else 414 info->max_p = 5; 415 info->max_p_usable = info->max_p; 416 } 417 418 return 0; 419 } 420