1 /* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #include <subdev/bios.h> 25 #include <subdev/bios/bit.h> 26 #include <subdev/bios/bmp.h> 27 #include <subdev/bios/pll.h> 28 #include <subdev/vga.h> 29 30 #include <core/device.h> 31 32 struct pll_mapping { 33 u8 type; 34 u32 reg; 35 }; 36 37 static struct pll_mapping 38 nv04_pll_mapping[] = { 39 { PLL_CORE , 0x680500 }, 40 { PLL_MEMORY, 0x680504 }, 41 { PLL_VPLL0 , 0x680508 }, 42 { PLL_VPLL1 , 0x680520 }, 43 {} 44 }; 45 46 static struct pll_mapping 47 nv40_pll_mapping[] = { 48 { PLL_CORE , 0x004000 }, 49 { PLL_MEMORY, 0x004020 }, 50 { PLL_VPLL0 , 0x680508 }, 51 { PLL_VPLL1 , 0x680520 }, 52 {} 53 }; 54 55 static struct pll_mapping 56 nv50_pll_mapping[] = { 57 { PLL_CORE , 0x004028 }, 58 { PLL_SHADER, 0x004020 }, 59 { PLL_UNK03 , 0x004000 }, 60 { PLL_MEMORY, 0x004008 }, 61 { PLL_UNK40 , 0x00e810 }, 62 { PLL_UNK41 , 0x00e818 }, 63 { PLL_UNK42 , 0x00e824 }, 64 { PLL_VPLL0 , 0x614100 }, 65 { PLL_VPLL1 , 0x614900 }, 66 {} 67 }; 68 69 static struct pll_mapping 70 g84_pll_mapping[] = { 71 { PLL_CORE , 0x004028 }, 72 { PLL_SHADER, 0x004020 }, 73 { PLL_MEMORY, 0x004008 }, 74 { PLL_VDEC , 0x004030 }, 75 { PLL_UNK41 , 0x00e818 }, 76 { PLL_VPLL0 , 0x614100 }, 77 { PLL_VPLL1 , 0x614900 }, 78 {} 79 }; 80 81 static u16 82 pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) 83 { 84 struct bit_entry bit_C; 85 86 if (!bit_entry(bios, 'C', &bit_C) && bit_C.length >= 10) { 87 u16 data = nv_ro16(bios, bit_C.offset + 8); 88 if (data) { 89 *ver = nv_ro08(bios, data + 0); 90 *hdr = nv_ro08(bios, data + 1); 91 *len = nv_ro08(bios, data + 2); 92 *cnt = nv_ro08(bios, data + 3); 93 return data; 94 } 95 } 96 97 if (bmp_version(bios) >= 0x0524) { 98 u16 data = nv_ro16(bios, bios->bmp_offset + 142); 99 if (data) { 100 *ver = nv_ro08(bios, data + 0); 101 *hdr = 1; 102 *cnt = 1; 103 *len = 0x18; 104 return data; 105 } 106 } 107 108 *ver = 0x00; 109 return 0x0000; 110 } 111 112 static struct pll_mapping * 113 pll_map(struct nvkm_bios *bios) 114 { 115 switch (nv_device(bios)->card_type) { 116 case NV_04: 117 case NV_10: 118 case NV_11: 119 case NV_20: 120 case NV_30: 121 return nv04_pll_mapping; 122 break; 123 case NV_40: 124 return nv40_pll_mapping; 125 case NV_50: 126 if (nv_device(bios)->chipset == 0x50) 127 return nv50_pll_mapping; 128 else 129 if (nv_device(bios)->chipset < 0xa3 || 130 nv_device(bios)->chipset == 0xaa || 131 nv_device(bios)->chipset == 0xac) 132 return g84_pll_mapping; 133 default: 134 return NULL; 135 } 136 } 137 138 static u16 139 pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) 140 { 141 struct pll_mapping *map; 142 u8 hdr, cnt; 143 u16 data; 144 145 data = pll_limits_table(bios, ver, &hdr, &cnt, len); 146 if (data && *ver >= 0x30) { 147 data += hdr; 148 while (cnt--) { 149 if (nv_ro32(bios, data + 3) == reg) { 150 *type = nv_ro08(bios, data + 0); 151 return data; 152 } 153 data += *len; 154 } 155 return 0x0000; 156 } 157 158 map = pll_map(bios); 159 while (map->reg) { 160 if (map->reg == reg && *ver >= 0x20) { 161 u16 addr = (data += hdr); 162 *type = map->type; 163 while (cnt--) { 164 if (nv_ro32(bios, data) == map->reg) 165 return data; 166 data += *len; 167 } 168 return addr; 169 } else 170 if (map->reg == reg) { 171 *type = map->type; 172 return data + 1; 173 } 174 map++; 175 } 176 177 return 0x0000; 178 } 179 180 static u16 181 pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) 182 { 183 struct pll_mapping *map; 184 u8 hdr, cnt; 185 u16 data; 186 187 data = pll_limits_table(bios, ver, &hdr, &cnt, len); 188 if (data && *ver >= 0x30) { 189 data += hdr; 190 while (cnt--) { 191 if (nv_ro08(bios, data + 0) == type) { 192 *reg = nv_ro32(bios, data + 3); 193 return data; 194 } 195 data += *len; 196 } 197 return 0x0000; 198 } 199 200 map = pll_map(bios); 201 while (map->reg) { 202 if (map->type == type && *ver >= 0x20) { 203 u16 addr = (data += hdr); 204 *reg = map->reg; 205 while (cnt--) { 206 if (nv_ro32(bios, data) == map->reg) 207 return data; 208 data += *len; 209 } 210 return addr; 211 } else 212 if (map->type == type) { 213 *reg = map->reg; 214 return data + 1; 215 } 216 map++; 217 } 218 219 return 0x0000; 220 } 221 222 int 223 nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info) 224 { 225 u8 ver, len; 226 u32 reg = type; 227 u16 data; 228 229 if (type > PLL_MAX) { 230 reg = type; 231 data = pll_map_reg(bios, reg, &type, &ver, &len); 232 } else { 233 data = pll_map_type(bios, type, ®, &ver, &len); 234 } 235 236 if (ver && !data) 237 return -ENOENT; 238 239 memset(info, 0, sizeof(*info)); 240 info->type = type; 241 info->reg = reg; 242 243 switch (ver) { 244 case 0x00: 245 break; 246 case 0x10: 247 case 0x11: 248 info->vco1.min_freq = nv_ro32(bios, data + 0); 249 info->vco1.max_freq = nv_ro32(bios, data + 4); 250 info->vco2.min_freq = nv_ro32(bios, data + 8); 251 info->vco2.max_freq = nv_ro32(bios, data + 12); 252 info->vco1.min_inputfreq = nv_ro32(bios, data + 16); 253 info->vco2.min_inputfreq = nv_ro32(bios, data + 20); 254 info->vco1.max_inputfreq = INT_MAX; 255 info->vco2.max_inputfreq = INT_MAX; 256 257 info->max_p = 0x7; 258 info->max_p_usable = 0x6; 259 260 /* these values taken from nv30/31/36 */ 261 switch (bios->version.chip) { 262 case 0x36: 263 info->vco1.min_n = 0x5; 264 break; 265 default: 266 info->vco1.min_n = 0x1; 267 break; 268 } 269 info->vco1.max_n = 0xff; 270 info->vco1.min_m = 0x1; 271 info->vco1.max_m = 0xd; 272 273 /* 274 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 275 * table version (apart from nv35)), N2 is compared to 276 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 277 * save a comparison 278 */ 279 info->vco2.min_n = 0x4; 280 switch (bios->version.chip) { 281 case 0x30: 282 case 0x35: 283 info->vco2.max_n = 0x1f; 284 break; 285 default: 286 info->vco2.max_n = 0x28; 287 break; 288 } 289 info->vco2.min_m = 0x1; 290 info->vco2.max_m = 0x4; 291 break; 292 case 0x20: 293 case 0x21: 294 info->vco1.min_freq = nv_ro16(bios, data + 4) * 1000; 295 info->vco1.max_freq = nv_ro16(bios, data + 6) * 1000; 296 info->vco2.min_freq = nv_ro16(bios, data + 8) * 1000; 297 info->vco2.max_freq = nv_ro16(bios, data + 10) * 1000; 298 info->vco1.min_inputfreq = nv_ro16(bios, data + 12) * 1000; 299 info->vco2.min_inputfreq = nv_ro16(bios, data + 14) * 1000; 300 info->vco1.max_inputfreq = nv_ro16(bios, data + 16) * 1000; 301 info->vco2.max_inputfreq = nv_ro16(bios, data + 18) * 1000; 302 info->vco1.min_n = nv_ro08(bios, data + 20); 303 info->vco1.max_n = nv_ro08(bios, data + 21); 304 info->vco1.min_m = nv_ro08(bios, data + 22); 305 info->vco1.max_m = nv_ro08(bios, data + 23); 306 info->vco2.min_n = nv_ro08(bios, data + 24); 307 info->vco2.max_n = nv_ro08(bios, data + 25); 308 info->vco2.min_m = nv_ro08(bios, data + 26); 309 info->vco2.max_m = nv_ro08(bios, data + 27); 310 311 info->max_p = nv_ro08(bios, data + 29); 312 info->max_p_usable = info->max_p; 313 if (bios->version.chip < 0x60) 314 info->max_p_usable = 0x6; 315 info->bias_p = nv_ro08(bios, data + 30); 316 317 if (len > 0x22) 318 info->refclk = nv_ro32(bios, data + 31); 319 break; 320 case 0x30: 321 data = nv_ro16(bios, data + 1); 322 323 info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000; 324 info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000; 325 info->vco2.min_freq = nv_ro16(bios, data + 4) * 1000; 326 info->vco2.max_freq = nv_ro16(bios, data + 6) * 1000; 327 info->vco1.min_inputfreq = nv_ro16(bios, data + 8) * 1000; 328 info->vco2.min_inputfreq = nv_ro16(bios, data + 10) * 1000; 329 info->vco1.max_inputfreq = nv_ro16(bios, data + 12) * 1000; 330 info->vco2.max_inputfreq = nv_ro16(bios, data + 14) * 1000; 331 info->vco1.min_n = nv_ro08(bios, data + 16); 332 info->vco1.max_n = nv_ro08(bios, data + 17); 333 info->vco1.min_m = nv_ro08(bios, data + 18); 334 info->vco1.max_m = nv_ro08(bios, data + 19); 335 info->vco2.min_n = nv_ro08(bios, data + 20); 336 info->vco2.max_n = nv_ro08(bios, data + 21); 337 info->vco2.min_m = nv_ro08(bios, data + 22); 338 info->vco2.max_m = nv_ro08(bios, data + 23); 339 info->max_p_usable = info->max_p = nv_ro08(bios, data + 25); 340 info->bias_p = nv_ro08(bios, data + 27); 341 info->refclk = nv_ro32(bios, data + 28); 342 break; 343 case 0x40: 344 info->refclk = nv_ro16(bios, data + 9) * 1000; 345 data = nv_ro16(bios, data + 1); 346 347 info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000; 348 info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000; 349 info->vco1.min_inputfreq = nv_ro16(bios, data + 4) * 1000; 350 info->vco1.max_inputfreq = nv_ro16(bios, data + 6) * 1000; 351 info->vco1.min_m = nv_ro08(bios, data + 8); 352 info->vco1.max_m = nv_ro08(bios, data + 9); 353 info->vco1.min_n = nv_ro08(bios, data + 10); 354 info->vco1.max_n = nv_ro08(bios, data + 11); 355 info->min_p = nv_ro08(bios, data + 12); 356 info->max_p = nv_ro08(bios, data + 13); 357 break; 358 default: 359 nv_error(bios, "unknown pll limits version 0x%02x\n", ver); 360 return -EINVAL; 361 } 362 363 if (!info->refclk) { 364 info->refclk = nv_device(bios)->crystal; 365 if (bios->version.chip == 0x51) { 366 u32 sel_clk = nv_rd32(bios, 0x680524); 367 if ((info->reg == 0x680508 && sel_clk & 0x20) || 368 (info->reg == 0x680520 && sel_clk & 0x80)) { 369 if (nv_rdvgac(bios, 0, 0x27) < 0xa3) 370 info->refclk = 200000; 371 else 372 info->refclk = 25000; 373 } 374 } 375 } 376 377 /* 378 * By now any valid limit table ought to have set a max frequency for 379 * vco1, so if it's zero it's either a pre limit table bios, or one 380 * with an empty limit table (seen on nv18) 381 */ 382 if (!info->vco1.max_freq) { 383 info->vco1.max_freq = nv_ro32(bios, bios->bmp_offset + 67); 384 info->vco1.min_freq = nv_ro32(bios, bios->bmp_offset + 71); 385 if (bmp_version(bios) < 0x0506) { 386 info->vco1.max_freq = 256000; 387 info->vco1.min_freq = 128000; 388 } 389 390 info->vco1.min_inputfreq = 0; 391 info->vco1.max_inputfreq = INT_MAX; 392 info->vco1.min_n = 0x1; 393 info->vco1.max_n = 0xff; 394 info->vco1.min_m = 0x1; 395 396 if (nv_device(bios)->crystal == 13500) { 397 /* nv05 does this, nv11 doesn't, nv10 unknown */ 398 if (bios->version.chip < 0x11) 399 info->vco1.min_m = 0x7; 400 info->vco1.max_m = 0xd; 401 } else { 402 if (bios->version.chip < 0x11) 403 info->vco1.min_m = 0x8; 404 info->vco1.max_m = 0xe; 405 } 406 407 if (bios->version.chip < 0x17 || 408 bios->version.chip == 0x1a || 409 bios->version.chip == 0x20) 410 info->max_p = 4; 411 else 412 info->max_p = 5; 413 info->max_p_usable = info->max_p; 414 } 415 416 return 0; 417 } 418