1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/bios.h> 25 #include <subdev/bios/bit.h> 26 #include <subdev/bios/bmp.h> 27 #include <subdev/bios/conn.h> 28 #include <subdev/bios/dcb.h> 29 #include <subdev/bios/dp.h> 30 #include <subdev/bios/gpio.h> 31 #include <subdev/bios/init.h> 32 #include <subdev/bios/ramcfg.h> 33 34 #include <subdev/devinit.h> 35 #include <subdev/gpio.h> 36 #include <subdev/i2c.h> 37 #include <subdev/vga.h> 38 39 #define bioslog(lvl, fmt, args...) do { \ 40 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \ 41 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \ 42 } while(0) 43 #define cont(fmt, args...) do { \ 44 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \ 45 printk(fmt, ##args); \ 46 } while(0) 47 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args) 48 #define warn(fmt, args...) bioslog(WARN, fmt, ##args) 49 #define error(fmt, args...) bioslog(ERROR, fmt, ##args) 50 51 /****************************************************************************** 52 * init parser control flow helpers 53 *****************************************************************************/ 54 55 static inline bool 56 init_exec(struct nvbios_init *init) 57 { 58 return (init->execute == 1) || ((init->execute & 5) == 5); 59 } 60 61 static inline void 62 init_exec_set(struct nvbios_init *init, bool exec) 63 { 64 if (exec) init->execute &= 0xfd; 65 else init->execute |= 0x02; 66 } 67 68 static inline void 69 init_exec_inv(struct nvbios_init *init) 70 { 71 init->execute ^= 0x02; 72 } 73 74 static inline void 75 init_exec_force(struct nvbios_init *init, bool exec) 76 { 77 if (exec) init->execute |= 0x04; 78 else init->execute &= 0xfb; 79 } 80 81 /****************************************************************************** 82 * init parser wrappers for normal register/i2c/whatever accessors 83 *****************************************************************************/ 84 85 static inline int 86 init_or(struct nvbios_init *init) 87 { 88 if (init_exec(init)) { 89 if (init->outp) 90 return ffs(init->outp->or) - 1; 91 error("script needs OR!!\n"); 92 } 93 return 0; 94 } 95 96 static inline int 97 init_link(struct nvbios_init *init) 98 { 99 if (init_exec(init)) { 100 if (init->outp) 101 return !(init->outp->sorconf.link & 1); 102 error("script needs OR link\n"); 103 } 104 return 0; 105 } 106 107 static inline int 108 init_crtc(struct nvbios_init *init) 109 { 110 if (init_exec(init)) { 111 if (init->crtc >= 0) 112 return init->crtc; 113 error("script needs crtc\n"); 114 } 115 return 0; 116 } 117 118 static u8 119 init_conn(struct nvbios_init *init) 120 { 121 struct nvkm_bios *bios = init->bios; 122 struct nvbios_connE connE; 123 u8 ver, hdr; 124 u32 conn; 125 126 if (init_exec(init)) { 127 if (init->outp) { 128 conn = init->outp->connector; 129 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE); 130 if (conn) 131 return connE.type; 132 } 133 134 error("script needs connector type\n"); 135 } 136 137 return 0xff; 138 } 139 140 static inline u32 141 init_nvreg(struct nvbios_init *init, u32 reg) 142 { 143 struct nvkm_devinit *devinit = nvkm_devinit(init->bios); 144 145 /* C51 (at least) sometimes has the lower bits set which the VBIOS 146 * interprets to mean that access needs to go through certain IO 147 * ports instead. The NVIDIA binary driver has been seen to access 148 * these through the NV register address, so lets assume we can 149 * do the same 150 */ 151 reg &= ~0x00000003; 152 153 /* GF8+ display scripts need register addresses mangled a bit to 154 * select a specific CRTC/OR 155 */ 156 if (nv_device(init->bios)->card_type >= NV_50) { 157 if (reg & 0x80000000) { 158 reg += init_crtc(init) * 0x800; 159 reg &= ~0x80000000; 160 } 161 162 if (reg & 0x40000000) { 163 reg += init_or(init) * 0x800; 164 reg &= ~0x40000000; 165 if (reg & 0x20000000) { 166 reg += init_link(init) * 0x80; 167 reg &= ~0x20000000; 168 } 169 } 170 } 171 172 if (reg & ~0x00fffffc) 173 warn("unknown bits in register 0x%08x\n", reg); 174 175 if (devinit->mmio) 176 reg = devinit->mmio(devinit, reg); 177 return reg; 178 } 179 180 static u32 181 init_rd32(struct nvbios_init *init, u32 reg) 182 { 183 reg = init_nvreg(init, reg); 184 if (reg != ~0 && init_exec(init)) 185 return nv_rd32(init->subdev, reg); 186 return 0x00000000; 187 } 188 189 static void 190 init_wr32(struct nvbios_init *init, u32 reg, u32 val) 191 { 192 reg = init_nvreg(init, reg); 193 if (reg != ~0 && init_exec(init)) 194 nv_wr32(init->subdev, reg, val); 195 } 196 197 static u32 198 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) 199 { 200 reg = init_nvreg(init, reg); 201 if (reg != ~0 && init_exec(init)) { 202 u32 tmp = nv_rd32(init->subdev, reg); 203 nv_wr32(init->subdev, reg, (tmp & ~mask) | val); 204 return tmp; 205 } 206 return 0x00000000; 207 } 208 209 static u8 210 init_rdport(struct nvbios_init *init, u16 port) 211 { 212 if (init_exec(init)) 213 return nv_rdport(init->subdev, init->crtc, port); 214 return 0x00; 215 } 216 217 static void 218 init_wrport(struct nvbios_init *init, u16 port, u8 value) 219 { 220 if (init_exec(init)) 221 nv_wrport(init->subdev, init->crtc, port, value); 222 } 223 224 static u8 225 init_rdvgai(struct nvbios_init *init, u16 port, u8 index) 226 { 227 struct nvkm_subdev *subdev = init->subdev; 228 if (init_exec(init)) { 229 int head = init->crtc < 0 ? 0 : init->crtc; 230 return nv_rdvgai(subdev, head, port, index); 231 } 232 return 0x00; 233 } 234 235 static void 236 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value) 237 { 238 /* force head 0 for updates to cr44, it only exists on first head */ 239 if (nv_device(init->subdev)->card_type < NV_50) { 240 if (port == 0x03d4 && index == 0x44) 241 init->crtc = 0; 242 } 243 244 if (init_exec(init)) { 245 int head = init->crtc < 0 ? 0 : init->crtc; 246 nv_wrvgai(init->subdev, head, port, index, value); 247 } 248 249 /* select head 1 if cr44 write selected it */ 250 if (nv_device(init->subdev)->card_type < NV_50) { 251 if (port == 0x03d4 && index == 0x44 && value == 3) 252 init->crtc = 1; 253 } 254 } 255 256 static struct nvkm_i2c_port * 257 init_i2c(struct nvbios_init *init, int index) 258 { 259 struct nvkm_i2c *i2c = nvkm_i2c(init->bios); 260 261 if (index == 0xff) { 262 index = NV_I2C_DEFAULT(0); 263 if (init->outp && init->outp->i2c_upper_default) 264 index = NV_I2C_DEFAULT(1); 265 } else 266 if (index < 0) { 267 if (!init->outp) { 268 if (init_exec(init)) 269 error("script needs output for i2c\n"); 270 return NULL; 271 } 272 273 if (index == -2 && init->outp->location) { 274 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev); 275 return i2c->find_type(i2c, index); 276 } 277 278 index = init->outp->i2c_index; 279 if (init->outp->type == DCB_OUTPUT_DP) 280 index += NV_I2C_AUX(0); 281 } 282 283 return i2c->find(i2c, index); 284 } 285 286 static int 287 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) 288 { 289 struct nvkm_i2c_port *port = init_i2c(init, index); 290 if (port && init_exec(init)) 291 return nv_rdi2cr(port, addr, reg); 292 return -ENODEV; 293 } 294 295 static int 296 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) 297 { 298 struct nvkm_i2c_port *port = init_i2c(init, index); 299 if (port && init_exec(init)) 300 return nv_wri2cr(port, addr, reg, val); 301 return -ENODEV; 302 } 303 304 static u8 305 init_rdauxr(struct nvbios_init *init, u32 addr) 306 { 307 struct nvkm_i2c_port *port = init_i2c(init, -2); 308 u8 data; 309 310 if (port && init_exec(init)) { 311 int ret = nv_rdaux(port, addr, &data, 1); 312 if (ret == 0) 313 return data; 314 trace("auxch read failed with %d\n", ret); 315 } 316 317 return 0x00; 318 } 319 320 static int 321 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) 322 { 323 struct nvkm_i2c_port *port = init_i2c(init, -2); 324 if (port && init_exec(init)) { 325 int ret = nv_wraux(port, addr, &data, 1); 326 if (ret) 327 trace("auxch write failed with %d\n", ret); 328 return ret; 329 } 330 return -ENODEV; 331 } 332 333 static void 334 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) 335 { 336 struct nvkm_devinit *devinit = nvkm_devinit(init->bios); 337 if (devinit->pll_set && init_exec(init)) { 338 int ret = devinit->pll_set(devinit, id, freq); 339 if (ret) 340 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq); 341 } 342 } 343 344 /****************************************************************************** 345 * parsing of bios structures that are required to execute init tables 346 *****************************************************************************/ 347 348 static u16 349 init_table(struct nvkm_bios *bios, u16 *len) 350 { 351 struct bit_entry bit_I; 352 353 if (!bit_entry(bios, 'I', &bit_I)) { 354 *len = bit_I.length; 355 return bit_I.offset; 356 } 357 358 if (bmp_version(bios) >= 0x0510) { 359 *len = 14; 360 return bios->bmp_offset + 75; 361 } 362 363 return 0x0000; 364 } 365 366 static u16 367 init_table_(struct nvbios_init *init, u16 offset, const char *name) 368 { 369 struct nvkm_bios *bios = init->bios; 370 u16 len, data = init_table(bios, &len); 371 if (data) { 372 if (len >= offset + 2) { 373 data = nv_ro16(bios, data + offset); 374 if (data) 375 return data; 376 377 warn("%s pointer invalid\n", name); 378 return 0x0000; 379 } 380 381 warn("init data too short for %s pointer", name); 382 return 0x0000; 383 } 384 385 warn("init data not found\n"); 386 return 0x0000; 387 } 388 389 #define init_script_table(b) init_table_((b), 0x00, "script table") 390 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table") 391 #define init_macro_table(b) init_table_((b), 0x04, "macro table") 392 #define init_condition_table(b) init_table_((b), 0x06, "condition table") 393 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table") 394 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table") 395 #define init_function_table(b) init_table_((b), 0x0c, "function table") 396 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); 397 398 static u16 399 init_script(struct nvkm_bios *bios, int index) 400 { 401 struct nvbios_init init = { .bios = bios }; 402 u16 bmp_ver = bmp_version(bios), data; 403 404 if (bmp_ver && bmp_ver < 0x0510) { 405 if (index > 1 || bmp_ver < 0x0100) 406 return 0x0000; 407 408 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18); 409 return nv_ro16(bios, data + (index * 2)); 410 } 411 412 data = init_script_table(&init); 413 if (data) 414 return nv_ro16(bios, data + (index * 2)); 415 416 return 0x0000; 417 } 418 419 static u16 420 init_unknown_script(struct nvkm_bios *bios) 421 { 422 u16 len, data = init_table(bios, &len); 423 if (data && len >= 16) 424 return nv_ro16(bios, data + 14); 425 return 0x0000; 426 } 427 428 static u8 429 init_ram_restrict_group_count(struct nvbios_init *init) 430 { 431 return nvbios_ramcfg_count(init->bios); 432 } 433 434 static u8 435 init_ram_restrict(struct nvbios_init *init) 436 { 437 /* This appears to be the behaviour of the VBIOS parser, and *is* 438 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to 439 * avoid fucking up the memory controller (somehow) by reading it 440 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode. 441 * 442 * Preserving the non-caching behaviour on earlier chipsets just 443 * in case *not* re-reading the strap causes similar breakage. 444 */ 445 if (!init->ramcfg || init->bios->version.major < 0x70) 446 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev); 447 return (init->ramcfg & 0x7fffffff); 448 } 449 450 static u8 451 init_xlat_(struct nvbios_init *init, u8 index, u8 offset) 452 { 453 struct nvkm_bios *bios = init->bios; 454 u16 table = init_xlat_table(init); 455 if (table) { 456 u16 data = nv_ro16(bios, table + (index * 2)); 457 if (data) 458 return nv_ro08(bios, data + offset); 459 warn("xlat table pointer %d invalid\n", index); 460 } 461 return 0x00; 462 } 463 464 /****************************************************************************** 465 * utility functions used by various init opcode handlers 466 *****************************************************************************/ 467 468 static bool 469 init_condition_met(struct nvbios_init *init, u8 cond) 470 { 471 struct nvkm_bios *bios = init->bios; 472 u16 table = init_condition_table(init); 473 if (table) { 474 u32 reg = nv_ro32(bios, table + (cond * 12) + 0); 475 u32 msk = nv_ro32(bios, table + (cond * 12) + 4); 476 u32 val = nv_ro32(bios, table + (cond * 12) + 8); 477 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n", 478 cond, reg, msk, val); 479 return (init_rd32(init, reg) & msk) == val; 480 } 481 return false; 482 } 483 484 static bool 485 init_io_condition_met(struct nvbios_init *init, u8 cond) 486 { 487 struct nvkm_bios *bios = init->bios; 488 u16 table = init_io_condition_table(init); 489 if (table) { 490 u16 port = nv_ro16(bios, table + (cond * 5) + 0); 491 u8 index = nv_ro08(bios, table + (cond * 5) + 2); 492 u8 mask = nv_ro08(bios, table + (cond * 5) + 3); 493 u8 value = nv_ro08(bios, table + (cond * 5) + 4); 494 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n", 495 cond, port, index, mask, value); 496 return (init_rdvgai(init, port, index) & mask) == value; 497 } 498 return false; 499 } 500 501 static bool 502 init_io_flag_condition_met(struct nvbios_init *init, u8 cond) 503 { 504 struct nvkm_bios *bios = init->bios; 505 u16 table = init_io_flag_condition_table(init); 506 if (table) { 507 u16 port = nv_ro16(bios, table + (cond * 9) + 0); 508 u8 index = nv_ro08(bios, table + (cond * 9) + 2); 509 u8 mask = nv_ro08(bios, table + (cond * 9) + 3); 510 u8 shift = nv_ro08(bios, table + (cond * 9) + 4); 511 u16 data = nv_ro16(bios, table + (cond * 9) + 5); 512 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7); 513 u8 value = nv_ro08(bios, table + (cond * 9) + 8); 514 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift; 515 return (nv_ro08(bios, data + ioval) & dmask) == value; 516 } 517 return false; 518 } 519 520 static inline u32 521 init_shift(u32 data, u8 shift) 522 { 523 if (shift < 0x80) 524 return data >> shift; 525 return data << (0x100 - shift); 526 } 527 528 static u32 529 init_tmds_reg(struct nvbios_init *init, u8 tmds) 530 { 531 /* For mlv < 0x80, it is an index into a table of TMDS base addresses. 532 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 533 * CR58 for CR57 = 0 to index a table of offsets to the basic 534 * 0x6808b0 address. 535 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 536 * CR58 for CR57 = 0 to index a table of offsets to the basic 537 * 0x6808b0 address, and then flip the offset by 8. 538 */ 539 const int pramdac_offset[13] = { 540 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 541 const u32 pramdac_table[4] = { 542 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 543 544 if (tmds >= 0x80) { 545 if (init->outp) { 546 u32 dacoffset = pramdac_offset[init->outp->or]; 547 if (tmds == 0x81) 548 dacoffset ^= 8; 549 return 0x6808b0 + dacoffset; 550 } 551 552 if (init_exec(init)) 553 error("tmds opcodes need dcb\n"); 554 } else { 555 if (tmds < ARRAY_SIZE(pramdac_table)) 556 return pramdac_table[tmds]; 557 558 error("tmds selector 0x%02x unknown\n", tmds); 559 } 560 561 return 0; 562 } 563 564 /****************************************************************************** 565 * init opcode handlers 566 *****************************************************************************/ 567 568 /** 569 * init_reserved - stub for various unknown/unused single-byte opcodes 570 * 571 */ 572 static void 573 init_reserved(struct nvbios_init *init) 574 { 575 u8 opcode = nv_ro08(init->bios, init->offset); 576 u8 length, i; 577 578 switch (opcode) { 579 case 0xaa: 580 length = 4; 581 break; 582 default: 583 length = 1; 584 break; 585 } 586 587 trace("RESERVED 0x%02x\t", opcode); 588 for (i = 1; i < length; i++) 589 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i)); 590 cont("\n"); 591 init->offset += length; 592 } 593 594 /** 595 * INIT_DONE - opcode 0x71 596 * 597 */ 598 static void 599 init_done(struct nvbios_init *init) 600 { 601 trace("DONE\n"); 602 init->offset = 0x0000; 603 } 604 605 /** 606 * INIT_IO_RESTRICT_PROG - opcode 0x32 607 * 608 */ 609 static void 610 init_io_restrict_prog(struct nvbios_init *init) 611 { 612 struct nvkm_bios *bios = init->bios; 613 u16 port = nv_ro16(bios, init->offset + 1); 614 u8 index = nv_ro08(bios, init->offset + 3); 615 u8 mask = nv_ro08(bios, init->offset + 4); 616 u8 shift = nv_ro08(bios, init->offset + 5); 617 u8 count = nv_ro08(bios, init->offset + 6); 618 u32 reg = nv_ro32(bios, init->offset + 7); 619 u8 conf, i; 620 621 trace("IO_RESTRICT_PROG\tR[0x%06x] = " 622 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n", 623 reg, port, index, mask, shift); 624 init->offset += 11; 625 626 conf = (init_rdvgai(init, port, index) & mask) >> shift; 627 for (i = 0; i < count; i++) { 628 u32 data = nv_ro32(bios, init->offset); 629 630 if (i == conf) { 631 trace("\t0x%08x *\n", data); 632 init_wr32(init, reg, data); 633 } else { 634 trace("\t0x%08x\n", data); 635 } 636 637 init->offset += 4; 638 } 639 trace("}]\n"); 640 } 641 642 /** 643 * INIT_REPEAT - opcode 0x33 644 * 645 */ 646 static void 647 init_repeat(struct nvbios_init *init) 648 { 649 struct nvkm_bios *bios = init->bios; 650 u8 count = nv_ro08(bios, init->offset + 1); 651 u16 repeat = init->repeat; 652 653 trace("REPEAT\t0x%02x\n", count); 654 init->offset += 2; 655 656 init->repeat = init->offset; 657 init->repend = init->offset; 658 while (count--) { 659 init->offset = init->repeat; 660 nvbios_exec(init); 661 if (count) 662 trace("REPEAT\t0x%02x\n", count); 663 } 664 init->offset = init->repend; 665 init->repeat = repeat; 666 } 667 668 /** 669 * INIT_IO_RESTRICT_PLL - opcode 0x34 670 * 671 */ 672 static void 673 init_io_restrict_pll(struct nvbios_init *init) 674 { 675 struct nvkm_bios *bios = init->bios; 676 u16 port = nv_ro16(bios, init->offset + 1); 677 u8 index = nv_ro08(bios, init->offset + 3); 678 u8 mask = nv_ro08(bios, init->offset + 4); 679 u8 shift = nv_ro08(bios, init->offset + 5); 680 s8 iofc = nv_ro08(bios, init->offset + 6); 681 u8 count = nv_ro08(bios, init->offset + 7); 682 u32 reg = nv_ro32(bios, init->offset + 8); 683 u8 conf, i; 684 685 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= " 686 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n", 687 reg, port, index, mask, shift, iofc); 688 init->offset += 12; 689 690 conf = (init_rdvgai(init, port, index) & mask) >> shift; 691 for (i = 0; i < count; i++) { 692 u32 freq = nv_ro16(bios, init->offset) * 10; 693 694 if (i == conf) { 695 trace("\t%dkHz *\n", freq); 696 if (iofc > 0 && init_io_flag_condition_met(init, iofc)) 697 freq *= 2; 698 init_prog_pll(init, reg, freq); 699 } else { 700 trace("\t%dkHz\n", freq); 701 } 702 703 init->offset += 2; 704 } 705 trace("}]\n"); 706 } 707 708 /** 709 * INIT_END_REPEAT - opcode 0x36 710 * 711 */ 712 static void 713 init_end_repeat(struct nvbios_init *init) 714 { 715 trace("END_REPEAT\n"); 716 init->offset += 1; 717 718 if (init->repeat) { 719 init->repend = init->offset; 720 init->offset = 0; 721 } 722 } 723 724 /** 725 * INIT_COPY - opcode 0x37 726 * 727 */ 728 static void 729 init_copy(struct nvbios_init *init) 730 { 731 struct nvkm_bios *bios = init->bios; 732 u32 reg = nv_ro32(bios, init->offset + 1); 733 u8 shift = nv_ro08(bios, init->offset + 5); 734 u8 smask = nv_ro08(bios, init->offset + 6); 735 u16 port = nv_ro16(bios, init->offset + 7); 736 u8 index = nv_ro08(bios, init->offset + 9); 737 u8 mask = nv_ro08(bios, init->offset + 10); 738 u8 data; 739 740 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= " 741 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n", 742 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", 743 (shift & 0x80) ? (0x100 - shift) : shift, smask); 744 init->offset += 11; 745 746 data = init_rdvgai(init, port, index) & mask; 747 data |= init_shift(init_rd32(init, reg), shift) & smask; 748 init_wrvgai(init, port, index, data); 749 } 750 751 /** 752 * INIT_NOT - opcode 0x38 753 * 754 */ 755 static void 756 init_not(struct nvbios_init *init) 757 { 758 trace("NOT\n"); 759 init->offset += 1; 760 init_exec_inv(init); 761 } 762 763 /** 764 * INIT_IO_FLAG_CONDITION - opcode 0x39 765 * 766 */ 767 static void 768 init_io_flag_condition(struct nvbios_init *init) 769 { 770 struct nvkm_bios *bios = init->bios; 771 u8 cond = nv_ro08(bios, init->offset + 1); 772 773 trace("IO_FLAG_CONDITION\t0x%02x\n", cond); 774 init->offset += 2; 775 776 if (!init_io_flag_condition_met(init, cond)) 777 init_exec_set(init, false); 778 } 779 780 /** 781 * INIT_DP_CONDITION - opcode 0x3a 782 * 783 */ 784 static void 785 init_dp_condition(struct nvbios_init *init) 786 { 787 struct nvkm_bios *bios = init->bios; 788 struct nvbios_dpout info; 789 u8 cond = nv_ro08(bios, init->offset + 1); 790 u8 unkn = nv_ro08(bios, init->offset + 2); 791 u8 ver, hdr, cnt, len; 792 u16 data; 793 794 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn); 795 init->offset += 3; 796 797 switch (cond) { 798 case 0: 799 if (init_conn(init) != DCB_CONNECTOR_eDP) 800 init_exec_set(init, false); 801 break; 802 case 1: 803 case 2: 804 if ( init->outp && 805 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP, 806 (init->outp->or << 0) | 807 (init->outp->sorconf.link << 6), 808 &ver, &hdr, &cnt, &len, &info))) 809 { 810 if (!(info.flags & cond)) 811 init_exec_set(init, false); 812 break; 813 } 814 815 if (init_exec(init)) 816 warn("script needs dp output table data\n"); 817 break; 818 case 5: 819 if (!(init_rdauxr(init, 0x0d) & 1)) 820 init_exec_set(init, false); 821 break; 822 default: 823 warn("unknown dp condition 0x%02x\n", cond); 824 break; 825 } 826 } 827 828 /** 829 * INIT_IO_MASK_OR - opcode 0x3b 830 * 831 */ 832 static void 833 init_io_mask_or(struct nvbios_init *init) 834 { 835 struct nvkm_bios *bios = init->bios; 836 u8 index = nv_ro08(bios, init->offset + 1); 837 u8 or = init_or(init); 838 u8 data; 839 840 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or); 841 init->offset += 2; 842 843 data = init_rdvgai(init, 0x03d4, index); 844 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); 845 } 846 847 /** 848 * INIT_IO_OR - opcode 0x3c 849 * 850 */ 851 static void 852 init_io_or(struct nvbios_init *init) 853 { 854 struct nvkm_bios *bios = init->bios; 855 u8 index = nv_ro08(bios, init->offset + 1); 856 u8 or = init_or(init); 857 u8 data; 858 859 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or); 860 init->offset += 2; 861 862 data = init_rdvgai(init, 0x03d4, index); 863 init_wrvgai(init, 0x03d4, index, data | (1 << or)); 864 } 865 866 /** 867 * INIT_ANDN_REG - opcode 0x47 868 * 869 */ 870 static void 871 init_andn_reg(struct nvbios_init *init) 872 { 873 struct nvkm_bios *bios = init->bios; 874 u32 reg = nv_ro32(bios, init->offset + 1); 875 u32 mask = nv_ro32(bios, init->offset + 5); 876 877 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask); 878 init->offset += 9; 879 880 init_mask(init, reg, mask, 0); 881 } 882 883 /** 884 * INIT_OR_REG - opcode 0x48 885 * 886 */ 887 static void 888 init_or_reg(struct nvbios_init *init) 889 { 890 struct nvkm_bios *bios = init->bios; 891 u32 reg = nv_ro32(bios, init->offset + 1); 892 u32 mask = nv_ro32(bios, init->offset + 5); 893 894 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask); 895 init->offset += 9; 896 897 init_mask(init, reg, 0, mask); 898 } 899 900 /** 901 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49 902 * 903 */ 904 static void 905 init_idx_addr_latched(struct nvbios_init *init) 906 { 907 struct nvkm_bios *bios = init->bios; 908 u32 creg = nv_ro32(bios, init->offset + 1); 909 u32 dreg = nv_ro32(bios, init->offset + 5); 910 u32 mask = nv_ro32(bios, init->offset + 9); 911 u32 data = nv_ro32(bios, init->offset + 13); 912 u8 count = nv_ro08(bios, init->offset + 17); 913 914 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg); 915 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data); 916 init->offset += 18; 917 918 while (count--) { 919 u8 iaddr = nv_ro08(bios, init->offset + 0); 920 u8 idata = nv_ro08(bios, init->offset + 1); 921 922 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata); 923 init->offset += 2; 924 925 init_wr32(init, dreg, idata); 926 init_mask(init, creg, ~mask, data | iaddr); 927 } 928 } 929 930 /** 931 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a 932 * 933 */ 934 static void 935 init_io_restrict_pll2(struct nvbios_init *init) 936 { 937 struct nvkm_bios *bios = init->bios; 938 u16 port = nv_ro16(bios, init->offset + 1); 939 u8 index = nv_ro08(bios, init->offset + 3); 940 u8 mask = nv_ro08(bios, init->offset + 4); 941 u8 shift = nv_ro08(bios, init->offset + 5); 942 u8 count = nv_ro08(bios, init->offset + 6); 943 u32 reg = nv_ro32(bios, init->offset + 7); 944 u8 conf, i; 945 946 trace("IO_RESTRICT_PLL2\t" 947 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n", 948 reg, port, index, mask, shift); 949 init->offset += 11; 950 951 conf = (init_rdvgai(init, port, index) & mask) >> shift; 952 for (i = 0; i < count; i++) { 953 u32 freq = nv_ro32(bios, init->offset); 954 if (i == conf) { 955 trace("\t%dkHz *\n", freq); 956 init_prog_pll(init, reg, freq); 957 } else { 958 trace("\t%dkHz\n", freq); 959 } 960 init->offset += 4; 961 } 962 trace("}]\n"); 963 } 964 965 /** 966 * INIT_PLL2 - opcode 0x4b 967 * 968 */ 969 static void 970 init_pll2(struct nvbios_init *init) 971 { 972 struct nvkm_bios *bios = init->bios; 973 u32 reg = nv_ro32(bios, init->offset + 1); 974 u32 freq = nv_ro32(bios, init->offset + 5); 975 976 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 977 init->offset += 9; 978 979 init_prog_pll(init, reg, freq); 980 } 981 982 /** 983 * INIT_I2C_BYTE - opcode 0x4c 984 * 985 */ 986 static void 987 init_i2c_byte(struct nvbios_init *init) 988 { 989 struct nvkm_bios *bios = init->bios; 990 u8 index = nv_ro08(bios, init->offset + 1); 991 u8 addr = nv_ro08(bios, init->offset + 2) >> 1; 992 u8 count = nv_ro08(bios, init->offset + 3); 993 994 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 995 init->offset += 4; 996 997 while (count--) { 998 u8 reg = nv_ro08(bios, init->offset + 0); 999 u8 mask = nv_ro08(bios, init->offset + 1); 1000 u8 data = nv_ro08(bios, init->offset + 2); 1001 int val; 1002 1003 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); 1004 init->offset += 3; 1005 1006 val = init_rdi2cr(init, index, addr, reg); 1007 if (val < 0) 1008 continue; 1009 init_wri2cr(init, index, addr, reg, (val & mask) | data); 1010 } 1011 } 1012 1013 /** 1014 * INIT_ZM_I2C_BYTE - opcode 0x4d 1015 * 1016 */ 1017 static void 1018 init_zm_i2c_byte(struct nvbios_init *init) 1019 { 1020 struct nvkm_bios *bios = init->bios; 1021 u8 index = nv_ro08(bios, init->offset + 1); 1022 u8 addr = nv_ro08(bios, init->offset + 2) >> 1; 1023 u8 count = nv_ro08(bios, init->offset + 3); 1024 1025 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 1026 init->offset += 4; 1027 1028 while (count--) { 1029 u8 reg = nv_ro08(bios, init->offset + 0); 1030 u8 data = nv_ro08(bios, init->offset + 1); 1031 1032 trace("\t[0x%02x] = 0x%02x\n", reg, data); 1033 init->offset += 2; 1034 1035 init_wri2cr(init, index, addr, reg, data); 1036 } 1037 } 1038 1039 /** 1040 * INIT_ZM_I2C - opcode 0x4e 1041 * 1042 */ 1043 static void 1044 init_zm_i2c(struct nvbios_init *init) 1045 { 1046 struct nvkm_bios *bios = init->bios; 1047 u8 index = nv_ro08(bios, init->offset + 1); 1048 u8 addr = nv_ro08(bios, init->offset + 2) >> 1; 1049 u8 count = nv_ro08(bios, init->offset + 3); 1050 u8 data[256], i; 1051 1052 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr); 1053 init->offset += 4; 1054 1055 for (i = 0; i < count; i++) { 1056 data[i] = nv_ro08(bios, init->offset); 1057 trace("\t0x%02x\n", data[i]); 1058 init->offset++; 1059 } 1060 1061 if (init_exec(init)) { 1062 struct nvkm_i2c_port *port = init_i2c(init, index); 1063 struct i2c_msg msg = { 1064 .addr = addr, .flags = 0, .len = count, .buf = data, 1065 }; 1066 int ret; 1067 1068 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1) 1069 warn("i2c wr failed, %d\n", ret); 1070 } 1071 } 1072 1073 /** 1074 * INIT_TMDS - opcode 0x4f 1075 * 1076 */ 1077 static void 1078 init_tmds(struct nvbios_init *init) 1079 { 1080 struct nvkm_bios *bios = init->bios; 1081 u8 tmds = nv_ro08(bios, init->offset + 1); 1082 u8 addr = nv_ro08(bios, init->offset + 2); 1083 u8 mask = nv_ro08(bios, init->offset + 3); 1084 u8 data = nv_ro08(bios, init->offset + 4); 1085 u32 reg = init_tmds_reg(init, tmds); 1086 1087 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n", 1088 tmds, addr, mask, data); 1089 init->offset += 5; 1090 1091 if (reg == 0) 1092 return; 1093 1094 init_wr32(init, reg + 0, addr | 0x00010000); 1095 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); 1096 init_wr32(init, reg + 0, addr); 1097 } 1098 1099 /** 1100 * INIT_ZM_TMDS_GROUP - opcode 0x50 1101 * 1102 */ 1103 static void 1104 init_zm_tmds_group(struct nvbios_init *init) 1105 { 1106 struct nvkm_bios *bios = init->bios; 1107 u8 tmds = nv_ro08(bios, init->offset + 1); 1108 u8 count = nv_ro08(bios, init->offset + 2); 1109 u32 reg = init_tmds_reg(init, tmds); 1110 1111 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds); 1112 init->offset += 3; 1113 1114 while (count--) { 1115 u8 addr = nv_ro08(bios, init->offset + 0); 1116 u8 data = nv_ro08(bios, init->offset + 1); 1117 1118 trace("\t[0x%02x] = 0x%02x\n", addr, data); 1119 init->offset += 2; 1120 1121 init_wr32(init, reg + 4, data); 1122 init_wr32(init, reg + 0, addr); 1123 } 1124 } 1125 1126 /** 1127 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51 1128 * 1129 */ 1130 static void 1131 init_cr_idx_adr_latch(struct nvbios_init *init) 1132 { 1133 struct nvkm_bios *bios = init->bios; 1134 u8 addr0 = nv_ro08(bios, init->offset + 1); 1135 u8 addr1 = nv_ro08(bios, init->offset + 2); 1136 u8 base = nv_ro08(bios, init->offset + 3); 1137 u8 count = nv_ro08(bios, init->offset + 4); 1138 u8 save0; 1139 1140 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1); 1141 init->offset += 5; 1142 1143 save0 = init_rdvgai(init, 0x03d4, addr0); 1144 while (count--) { 1145 u8 data = nv_ro08(bios, init->offset); 1146 1147 trace("\t\t[0x%02x] = 0x%02x\n", base, data); 1148 init->offset += 1; 1149 1150 init_wrvgai(init, 0x03d4, addr0, base++); 1151 init_wrvgai(init, 0x03d4, addr1, data); 1152 } 1153 init_wrvgai(init, 0x03d4, addr0, save0); 1154 } 1155 1156 /** 1157 * INIT_CR - opcode 0x52 1158 * 1159 */ 1160 static void 1161 init_cr(struct nvbios_init *init) 1162 { 1163 struct nvkm_bios *bios = init->bios; 1164 u8 addr = nv_ro08(bios, init->offset + 1); 1165 u8 mask = nv_ro08(bios, init->offset + 2); 1166 u8 data = nv_ro08(bios, init->offset + 3); 1167 u8 val; 1168 1169 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 1170 init->offset += 4; 1171 1172 val = init_rdvgai(init, 0x03d4, addr) & mask; 1173 init_wrvgai(init, 0x03d4, addr, val | data); 1174 } 1175 1176 /** 1177 * INIT_ZM_CR - opcode 0x53 1178 * 1179 */ 1180 static void 1181 init_zm_cr(struct nvbios_init *init) 1182 { 1183 struct nvkm_bios *bios = init->bios; 1184 u8 addr = nv_ro08(bios, init->offset + 1); 1185 u8 data = nv_ro08(bios, init->offset + 2); 1186 1187 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data); 1188 init->offset += 3; 1189 1190 init_wrvgai(init, 0x03d4, addr, data); 1191 } 1192 1193 /** 1194 * INIT_ZM_CR_GROUP - opcode 0x54 1195 * 1196 */ 1197 static void 1198 init_zm_cr_group(struct nvbios_init *init) 1199 { 1200 struct nvkm_bios *bios = init->bios; 1201 u8 count = nv_ro08(bios, init->offset + 1); 1202 1203 trace("ZM_CR_GROUP\n"); 1204 init->offset += 2; 1205 1206 while (count--) { 1207 u8 addr = nv_ro08(bios, init->offset + 0); 1208 u8 data = nv_ro08(bios, init->offset + 1); 1209 1210 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data); 1211 init->offset += 2; 1212 1213 init_wrvgai(init, 0x03d4, addr, data); 1214 } 1215 } 1216 1217 /** 1218 * INIT_CONDITION_TIME - opcode 0x56 1219 * 1220 */ 1221 static void 1222 init_condition_time(struct nvbios_init *init) 1223 { 1224 struct nvkm_bios *bios = init->bios; 1225 u8 cond = nv_ro08(bios, init->offset + 1); 1226 u8 retry = nv_ro08(bios, init->offset + 2); 1227 u8 wait = min((u16)retry * 50, 100); 1228 1229 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry); 1230 init->offset += 3; 1231 1232 if (!init_exec(init)) 1233 return; 1234 1235 while (wait--) { 1236 if (init_condition_met(init, cond)) 1237 return; 1238 mdelay(20); 1239 } 1240 1241 init_exec_set(init, false); 1242 } 1243 1244 /** 1245 * INIT_LTIME - opcode 0x57 1246 * 1247 */ 1248 static void 1249 init_ltime(struct nvbios_init *init) 1250 { 1251 struct nvkm_bios *bios = init->bios; 1252 u16 msec = nv_ro16(bios, init->offset + 1); 1253 1254 trace("LTIME\t0x%04x\n", msec); 1255 init->offset += 3; 1256 1257 if (init_exec(init)) 1258 mdelay(msec); 1259 } 1260 1261 /** 1262 * INIT_ZM_REG_SEQUENCE - opcode 0x58 1263 * 1264 */ 1265 static void 1266 init_zm_reg_sequence(struct nvbios_init *init) 1267 { 1268 struct nvkm_bios *bios = init->bios; 1269 u32 base = nv_ro32(bios, init->offset + 1); 1270 u8 count = nv_ro08(bios, init->offset + 5); 1271 1272 trace("ZM_REG_SEQUENCE\t0x%02x\n", count); 1273 init->offset += 6; 1274 1275 while (count--) { 1276 u32 data = nv_ro32(bios, init->offset); 1277 1278 trace("\t\tR[0x%06x] = 0x%08x\n", base, data); 1279 init->offset += 4; 1280 1281 init_wr32(init, base, data); 1282 base += 4; 1283 } 1284 } 1285 1286 /** 1287 * INIT_PLL_INDIRECT - opcode 0x59 1288 * 1289 */ 1290 static void 1291 init_pll_indirect(struct nvbios_init *init) 1292 { 1293 struct nvkm_bios *bios = init->bios; 1294 u32 reg = nv_ro32(bios, init->offset + 1); 1295 u16 addr = nv_ro16(bios, init->offset + 5); 1296 u32 freq = (u32)nv_ro16(bios, addr) * 1000; 1297 1298 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n", 1299 reg, addr, freq); 1300 init->offset += 7; 1301 1302 init_prog_pll(init, reg, freq); 1303 } 1304 1305 /** 1306 * INIT_ZM_REG_INDIRECT - opcode 0x5a 1307 * 1308 */ 1309 static void 1310 init_zm_reg_indirect(struct nvbios_init *init) 1311 { 1312 struct nvkm_bios *bios = init->bios; 1313 u32 reg = nv_ro32(bios, init->offset + 1); 1314 u16 addr = nv_ro16(bios, init->offset + 5); 1315 u32 data = nv_ro32(bios, addr); 1316 1317 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n", 1318 reg, addr, data); 1319 init->offset += 7; 1320 1321 init_wr32(init, addr, data); 1322 } 1323 1324 /** 1325 * INIT_SUB_DIRECT - opcode 0x5b 1326 * 1327 */ 1328 static void 1329 init_sub_direct(struct nvbios_init *init) 1330 { 1331 struct nvkm_bios *bios = init->bios; 1332 u16 addr = nv_ro16(bios, init->offset + 1); 1333 u16 save; 1334 1335 trace("SUB_DIRECT\t0x%04x\n", addr); 1336 1337 if (init_exec(init)) { 1338 save = init->offset; 1339 init->offset = addr; 1340 if (nvbios_exec(init)) { 1341 error("error parsing sub-table\n"); 1342 return; 1343 } 1344 init->offset = save; 1345 } 1346 1347 init->offset += 3; 1348 } 1349 1350 /** 1351 * INIT_JUMP - opcode 0x5c 1352 * 1353 */ 1354 static void 1355 init_jump(struct nvbios_init *init) 1356 { 1357 struct nvkm_bios *bios = init->bios; 1358 u16 offset = nv_ro16(bios, init->offset + 1); 1359 1360 trace("JUMP\t0x%04x\n", offset); 1361 1362 if (init_exec(init)) 1363 init->offset = offset; 1364 else 1365 init->offset += 3; 1366 } 1367 1368 /** 1369 * INIT_I2C_IF - opcode 0x5e 1370 * 1371 */ 1372 static void 1373 init_i2c_if(struct nvbios_init *init) 1374 { 1375 struct nvkm_bios *bios = init->bios; 1376 u8 index = nv_ro08(bios, init->offset + 1); 1377 u8 addr = nv_ro08(bios, init->offset + 2); 1378 u8 reg = nv_ro08(bios, init->offset + 3); 1379 u8 mask = nv_ro08(bios, init->offset + 4); 1380 u8 data = nv_ro08(bios, init->offset + 5); 1381 u8 value; 1382 1383 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n", 1384 index, addr, reg, mask, data); 1385 init->offset += 6; 1386 init_exec_force(init, true); 1387 1388 value = init_rdi2cr(init, index, addr, reg); 1389 if ((value & mask) != data) 1390 init_exec_set(init, false); 1391 1392 init_exec_force(init, false); 1393 } 1394 1395 /** 1396 * INIT_COPY_NV_REG - opcode 0x5f 1397 * 1398 */ 1399 static void 1400 init_copy_nv_reg(struct nvbios_init *init) 1401 { 1402 struct nvkm_bios *bios = init->bios; 1403 u32 sreg = nv_ro32(bios, init->offset + 1); 1404 u8 shift = nv_ro08(bios, init->offset + 5); 1405 u32 smask = nv_ro32(bios, init->offset + 6); 1406 u32 sxor = nv_ro32(bios, init->offset + 10); 1407 u32 dreg = nv_ro32(bios, init->offset + 14); 1408 u32 dmask = nv_ro32(bios, init->offset + 18); 1409 u32 data; 1410 1411 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= " 1412 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n", 1413 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>", 1414 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor); 1415 init->offset += 22; 1416 1417 data = init_shift(init_rd32(init, sreg), shift); 1418 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor); 1419 } 1420 1421 /** 1422 * INIT_ZM_INDEX_IO - opcode 0x62 1423 * 1424 */ 1425 static void 1426 init_zm_index_io(struct nvbios_init *init) 1427 { 1428 struct nvkm_bios *bios = init->bios; 1429 u16 port = nv_ro16(bios, init->offset + 1); 1430 u8 index = nv_ro08(bios, init->offset + 3); 1431 u8 data = nv_ro08(bios, init->offset + 4); 1432 1433 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data); 1434 init->offset += 5; 1435 1436 init_wrvgai(init, port, index, data); 1437 } 1438 1439 /** 1440 * INIT_COMPUTE_MEM - opcode 0x63 1441 * 1442 */ 1443 static void 1444 init_compute_mem(struct nvbios_init *init) 1445 { 1446 struct nvkm_devinit *devinit = nvkm_devinit(init->bios); 1447 1448 trace("COMPUTE_MEM\n"); 1449 init->offset += 1; 1450 1451 init_exec_force(init, true); 1452 if (init_exec(init) && devinit->meminit) 1453 devinit->meminit(devinit); 1454 init_exec_force(init, false); 1455 } 1456 1457 /** 1458 * INIT_RESET - opcode 0x65 1459 * 1460 */ 1461 static void 1462 init_reset(struct nvbios_init *init) 1463 { 1464 struct nvkm_bios *bios = init->bios; 1465 u32 reg = nv_ro32(bios, init->offset + 1); 1466 u32 data1 = nv_ro32(bios, init->offset + 5); 1467 u32 data2 = nv_ro32(bios, init->offset + 9); 1468 u32 savepci19; 1469 1470 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2); 1471 init->offset += 13; 1472 init_exec_force(init, true); 1473 1474 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000); 1475 init_wr32(init, reg, data1); 1476 udelay(10); 1477 init_wr32(init, reg, data2); 1478 init_wr32(init, 0x00184c, savepci19); 1479 init_mask(init, 0x001850, 0x00000001, 0x00000000); 1480 1481 init_exec_force(init, false); 1482 } 1483 1484 /** 1485 * INIT_CONFIGURE_MEM - opcode 0x66 1486 * 1487 */ 1488 static u16 1489 init_configure_mem_clk(struct nvbios_init *init) 1490 { 1491 u16 mdata = bmp_mem_init_table(init->bios); 1492 if (mdata) 1493 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66; 1494 return mdata; 1495 } 1496 1497 static void 1498 init_configure_mem(struct nvbios_init *init) 1499 { 1500 struct nvkm_bios *bios = init->bios; 1501 u16 mdata, sdata; 1502 u32 addr, data; 1503 1504 trace("CONFIGURE_MEM\n"); 1505 init->offset += 1; 1506 1507 if (bios->version.major > 2) { 1508 init_done(init); 1509 return; 1510 } 1511 init_exec_force(init, true); 1512 1513 mdata = init_configure_mem_clk(init); 1514 sdata = bmp_sdr_seq_table(bios); 1515 if (nv_ro08(bios, mdata) & 0x01) 1516 sdata = bmp_ddr_seq_table(bios); 1517 mdata += 6; /* skip to data */ 1518 1519 data = init_rdvgai(init, 0x03c4, 0x01); 1520 init_wrvgai(init, 0x03c4, 0x01, data | 0x20); 1521 1522 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) { 1523 switch (addr) { 1524 case 0x10021c: /* CKE_NORMAL */ 1525 case 0x1002d0: /* CMD_REFRESH */ 1526 case 0x1002d4: /* CMD_PRECHARGE */ 1527 data = 0x00000001; 1528 break; 1529 default: 1530 data = nv_ro32(bios, mdata); 1531 mdata += 4; 1532 if (data == 0xffffffff) 1533 continue; 1534 break; 1535 } 1536 1537 init_wr32(init, addr, data); 1538 } 1539 1540 init_exec_force(init, false); 1541 } 1542 1543 /** 1544 * INIT_CONFIGURE_CLK - opcode 0x67 1545 * 1546 */ 1547 static void 1548 init_configure_clk(struct nvbios_init *init) 1549 { 1550 struct nvkm_bios *bios = init->bios; 1551 u16 mdata, clock; 1552 1553 trace("CONFIGURE_CLK\n"); 1554 init->offset += 1; 1555 1556 if (bios->version.major > 2) { 1557 init_done(init); 1558 return; 1559 } 1560 init_exec_force(init, true); 1561 1562 mdata = init_configure_mem_clk(init); 1563 1564 /* NVPLL */ 1565 clock = nv_ro16(bios, mdata + 4) * 10; 1566 init_prog_pll(init, 0x680500, clock); 1567 1568 /* MPLL */ 1569 clock = nv_ro16(bios, mdata + 2) * 10; 1570 if (nv_ro08(bios, mdata) & 0x01) 1571 clock *= 2; 1572 init_prog_pll(init, 0x680504, clock); 1573 1574 init_exec_force(init, false); 1575 } 1576 1577 /** 1578 * INIT_CONFIGURE_PREINIT - opcode 0x68 1579 * 1580 */ 1581 static void 1582 init_configure_preinit(struct nvbios_init *init) 1583 { 1584 struct nvkm_bios *bios = init->bios; 1585 u32 strap; 1586 1587 trace("CONFIGURE_PREINIT\n"); 1588 init->offset += 1; 1589 1590 if (bios->version.major > 2) { 1591 init_done(init); 1592 return; 1593 } 1594 init_exec_force(init, true); 1595 1596 strap = init_rd32(init, 0x101000); 1597 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6); 1598 init_wrvgai(init, 0x03d4, 0x3c, strap); 1599 1600 init_exec_force(init, false); 1601 } 1602 1603 /** 1604 * INIT_IO - opcode 0x69 1605 * 1606 */ 1607 static void 1608 init_io(struct nvbios_init *init) 1609 { 1610 struct nvkm_bios *bios = init->bios; 1611 u16 port = nv_ro16(bios, init->offset + 1); 1612 u8 mask = nv_ro16(bios, init->offset + 3); 1613 u8 data = nv_ro16(bios, init->offset + 4); 1614 u8 value; 1615 1616 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data); 1617 init->offset += 5; 1618 1619 /* ummm.. yes.. should really figure out wtf this is and why it's 1620 * needed some day.. it's almost certainly wrong, but, it also 1621 * somehow makes things work... 1622 */ 1623 if (nv_device(init->bios)->card_type >= NV_50 && 1624 port == 0x03c3 && data == 0x01) { 1625 init_mask(init, 0x614100, 0xf0800000, 0x00800000); 1626 init_mask(init, 0x00e18c, 0x00020000, 0x00020000); 1627 init_mask(init, 0x614900, 0xf0800000, 0x00800000); 1628 init_mask(init, 0x000200, 0x40000000, 0x00000000); 1629 mdelay(10); 1630 init_mask(init, 0x00e18c, 0x00020000, 0x00000000); 1631 init_mask(init, 0x000200, 0x40000000, 0x40000000); 1632 init_wr32(init, 0x614100, 0x00800018); 1633 init_wr32(init, 0x614900, 0x00800018); 1634 mdelay(10); 1635 init_wr32(init, 0x614100, 0x10000018); 1636 init_wr32(init, 0x614900, 0x10000018); 1637 } 1638 1639 value = init_rdport(init, port) & mask; 1640 init_wrport(init, port, data | value); 1641 } 1642 1643 /** 1644 * INIT_SUB - opcode 0x6b 1645 * 1646 */ 1647 static void 1648 init_sub(struct nvbios_init *init) 1649 { 1650 struct nvkm_bios *bios = init->bios; 1651 u8 index = nv_ro08(bios, init->offset + 1); 1652 u16 addr, save; 1653 1654 trace("SUB\t0x%02x\n", index); 1655 1656 addr = init_script(bios, index); 1657 if (addr && init_exec(init)) { 1658 save = init->offset; 1659 init->offset = addr; 1660 if (nvbios_exec(init)) { 1661 error("error parsing sub-table\n"); 1662 return; 1663 } 1664 init->offset = save; 1665 } 1666 1667 init->offset += 2; 1668 } 1669 1670 /** 1671 * INIT_RAM_CONDITION - opcode 0x6d 1672 * 1673 */ 1674 static void 1675 init_ram_condition(struct nvbios_init *init) 1676 { 1677 struct nvkm_bios *bios = init->bios; 1678 u8 mask = nv_ro08(bios, init->offset + 1); 1679 u8 value = nv_ro08(bios, init->offset + 2); 1680 1681 trace("RAM_CONDITION\t" 1682 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value); 1683 init->offset += 3; 1684 1685 if ((init_rd32(init, 0x100000) & mask) != value) 1686 init_exec_set(init, false); 1687 } 1688 1689 /** 1690 * INIT_NV_REG - opcode 0x6e 1691 * 1692 */ 1693 static void 1694 init_nv_reg(struct nvbios_init *init) 1695 { 1696 struct nvkm_bios *bios = init->bios; 1697 u32 reg = nv_ro32(bios, init->offset + 1); 1698 u32 mask = nv_ro32(bios, init->offset + 5); 1699 u32 data = nv_ro32(bios, init->offset + 9); 1700 1701 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); 1702 init->offset += 13; 1703 1704 init_mask(init, reg, ~mask, data); 1705 } 1706 1707 /** 1708 * INIT_MACRO - opcode 0x6f 1709 * 1710 */ 1711 static void 1712 init_macro(struct nvbios_init *init) 1713 { 1714 struct nvkm_bios *bios = init->bios; 1715 u8 macro = nv_ro08(bios, init->offset + 1); 1716 u16 table; 1717 1718 trace("MACRO\t0x%02x\n", macro); 1719 1720 table = init_macro_table(init); 1721 if (table) { 1722 u32 addr = nv_ro32(bios, table + (macro * 8) + 0); 1723 u32 data = nv_ro32(bios, table + (macro * 8) + 4); 1724 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data); 1725 init_wr32(init, addr, data); 1726 } 1727 1728 init->offset += 2; 1729 } 1730 1731 /** 1732 * INIT_RESUME - opcode 0x72 1733 * 1734 */ 1735 static void 1736 init_resume(struct nvbios_init *init) 1737 { 1738 trace("RESUME\n"); 1739 init->offset += 1; 1740 init_exec_set(init, true); 1741 } 1742 1743 /** 1744 * INIT_STRAP_CONDITION - opcode 0x73 1745 * 1746 */ 1747 static void 1748 init_strap_condition(struct nvbios_init *init) 1749 { 1750 struct nvkm_bios *bios = init->bios; 1751 u32 mask = nv_ro32(bios, init->offset + 1); 1752 u32 value = nv_ro32(bios, init->offset + 5); 1753 1754 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value); 1755 init->offset += 9; 1756 1757 if ((init_rd32(init, 0x101000) & mask) != value) 1758 init_exec_set(init, false); 1759 } 1760 1761 /** 1762 * INIT_TIME - opcode 0x74 1763 * 1764 */ 1765 static void 1766 init_time(struct nvbios_init *init) 1767 { 1768 struct nvkm_bios *bios = init->bios; 1769 u16 usec = nv_ro16(bios, init->offset + 1); 1770 1771 trace("TIME\t0x%04x\n", usec); 1772 init->offset += 3; 1773 1774 if (init_exec(init)) { 1775 if (usec < 1000) 1776 udelay(usec); 1777 else 1778 mdelay((usec + 900) / 1000); 1779 } 1780 } 1781 1782 /** 1783 * INIT_CONDITION - opcode 0x75 1784 * 1785 */ 1786 static void 1787 init_condition(struct nvbios_init *init) 1788 { 1789 struct nvkm_bios *bios = init->bios; 1790 u8 cond = nv_ro08(bios, init->offset + 1); 1791 1792 trace("CONDITION\t0x%02x\n", cond); 1793 init->offset += 2; 1794 1795 if (!init_condition_met(init, cond)) 1796 init_exec_set(init, false); 1797 } 1798 1799 /** 1800 * INIT_IO_CONDITION - opcode 0x76 1801 * 1802 */ 1803 static void 1804 init_io_condition(struct nvbios_init *init) 1805 { 1806 struct nvkm_bios *bios = init->bios; 1807 u8 cond = nv_ro08(bios, init->offset + 1); 1808 1809 trace("IO_CONDITION\t0x%02x\n", cond); 1810 init->offset += 2; 1811 1812 if (!init_io_condition_met(init, cond)) 1813 init_exec_set(init, false); 1814 } 1815 1816 /** 1817 * INIT_ZM_REG16 - opcode 0x77 1818 * 1819 */ 1820 static void 1821 init_zm_reg16(struct nvbios_init *init) 1822 { 1823 struct nvkm_bios *bios = init->bios; 1824 u32 addr = nv_ro32(bios, init->offset + 1); 1825 u16 data = nv_ro16(bios, init->offset + 5); 1826 1827 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data); 1828 init->offset += 7; 1829 1830 init_wr32(init, addr, data); 1831 } 1832 1833 /** 1834 * INIT_INDEX_IO - opcode 0x78 1835 * 1836 */ 1837 static void 1838 init_index_io(struct nvbios_init *init) 1839 { 1840 struct nvkm_bios *bios = init->bios; 1841 u16 port = nv_ro16(bios, init->offset + 1); 1842 u8 index = nv_ro16(bios, init->offset + 3); 1843 u8 mask = nv_ro08(bios, init->offset + 4); 1844 u8 data = nv_ro08(bios, init->offset + 5); 1845 u8 value; 1846 1847 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n", 1848 port, index, mask, data); 1849 init->offset += 6; 1850 1851 value = init_rdvgai(init, port, index) & mask; 1852 init_wrvgai(init, port, index, data | value); 1853 } 1854 1855 /** 1856 * INIT_PLL - opcode 0x79 1857 * 1858 */ 1859 static void 1860 init_pll(struct nvbios_init *init) 1861 { 1862 struct nvkm_bios *bios = init->bios; 1863 u32 reg = nv_ro32(bios, init->offset + 1); 1864 u32 freq = nv_ro16(bios, init->offset + 5) * 10; 1865 1866 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 1867 init->offset += 7; 1868 1869 init_prog_pll(init, reg, freq); 1870 } 1871 1872 /** 1873 * INIT_ZM_REG - opcode 0x7a 1874 * 1875 */ 1876 static void 1877 init_zm_reg(struct nvbios_init *init) 1878 { 1879 struct nvkm_bios *bios = init->bios; 1880 u32 addr = nv_ro32(bios, init->offset + 1); 1881 u32 data = nv_ro32(bios, init->offset + 5); 1882 1883 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data); 1884 init->offset += 9; 1885 1886 if (addr == 0x000200) 1887 data |= 0x00000001; 1888 1889 init_wr32(init, addr, data); 1890 } 1891 1892 /** 1893 * INIT_RAM_RESTRICT_PLL - opcde 0x87 1894 * 1895 */ 1896 static void 1897 init_ram_restrict_pll(struct nvbios_init *init) 1898 { 1899 struct nvkm_bios *bios = init->bios; 1900 u8 type = nv_ro08(bios, init->offset + 1); 1901 u8 count = init_ram_restrict_group_count(init); 1902 u8 strap = init_ram_restrict(init); 1903 u8 cconf; 1904 1905 trace("RAM_RESTRICT_PLL\t0x%02x\n", type); 1906 init->offset += 2; 1907 1908 for (cconf = 0; cconf < count; cconf++) { 1909 u32 freq = nv_ro32(bios, init->offset); 1910 1911 if (cconf == strap) { 1912 trace("%dkHz *\n", freq); 1913 init_prog_pll(init, type, freq); 1914 } else { 1915 trace("%dkHz\n", freq); 1916 } 1917 1918 init->offset += 4; 1919 } 1920 } 1921 1922 /** 1923 * INIT_GPIO - opcode 0x8e 1924 * 1925 */ 1926 static void 1927 init_gpio(struct nvbios_init *init) 1928 { 1929 struct nvkm_gpio *gpio = nvkm_gpio(init->bios); 1930 1931 trace("GPIO\n"); 1932 init->offset += 1; 1933 1934 if (init_exec(init) && gpio && gpio->reset) 1935 gpio->reset(gpio, DCB_GPIO_UNUSED); 1936 } 1937 1938 /** 1939 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f 1940 * 1941 */ 1942 static void 1943 init_ram_restrict_zm_reg_group(struct nvbios_init *init) 1944 { 1945 struct nvkm_bios *bios = init->bios; 1946 u32 addr = nv_ro32(bios, init->offset + 1); 1947 u8 incr = nv_ro08(bios, init->offset + 5); 1948 u8 num = nv_ro08(bios, init->offset + 6); 1949 u8 count = init_ram_restrict_group_count(init); 1950 u8 index = init_ram_restrict(init); 1951 u8 i, j; 1952 1953 trace("RAM_RESTRICT_ZM_REG_GROUP\t" 1954 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num); 1955 init->offset += 7; 1956 1957 for (i = 0; i < num; i++) { 1958 trace("\tR[0x%06x] = {\n", addr); 1959 for (j = 0; j < count; j++) { 1960 u32 data = nv_ro32(bios, init->offset); 1961 1962 if (j == index) { 1963 trace("\t\t0x%08x *\n", data); 1964 init_wr32(init, addr, data); 1965 } else { 1966 trace("\t\t0x%08x\n", data); 1967 } 1968 1969 init->offset += 4; 1970 } 1971 trace("\t}\n"); 1972 addr += incr; 1973 } 1974 } 1975 1976 /** 1977 * INIT_COPY_ZM_REG - opcode 0x90 1978 * 1979 */ 1980 static void 1981 init_copy_zm_reg(struct nvbios_init *init) 1982 { 1983 struct nvkm_bios *bios = init->bios; 1984 u32 sreg = nv_ro32(bios, init->offset + 1); 1985 u32 dreg = nv_ro32(bios, init->offset + 5); 1986 1987 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg); 1988 init->offset += 9; 1989 1990 init_wr32(init, dreg, init_rd32(init, sreg)); 1991 } 1992 1993 /** 1994 * INIT_ZM_REG_GROUP - opcode 0x91 1995 * 1996 */ 1997 static void 1998 init_zm_reg_group(struct nvbios_init *init) 1999 { 2000 struct nvkm_bios *bios = init->bios; 2001 u32 addr = nv_ro32(bios, init->offset + 1); 2002 u8 count = nv_ro08(bios, init->offset + 5); 2003 2004 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr); 2005 init->offset += 6; 2006 2007 while (count--) { 2008 u32 data = nv_ro32(bios, init->offset); 2009 trace("\t0x%08x\n", data); 2010 init_wr32(init, addr, data); 2011 init->offset += 4; 2012 } 2013 } 2014 2015 /** 2016 * INIT_XLAT - opcode 0x96 2017 * 2018 */ 2019 static void 2020 init_xlat(struct nvbios_init *init) 2021 { 2022 struct nvkm_bios *bios = init->bios; 2023 u32 saddr = nv_ro32(bios, init->offset + 1); 2024 u8 sshift = nv_ro08(bios, init->offset + 5); 2025 u8 smask = nv_ro08(bios, init->offset + 6); 2026 u8 index = nv_ro08(bios, init->offset + 7); 2027 u32 daddr = nv_ro32(bios, init->offset + 8); 2028 u32 dmask = nv_ro32(bios, init->offset + 12); 2029 u8 shift = nv_ro08(bios, init->offset + 16); 2030 u32 data; 2031 2032 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= " 2033 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n", 2034 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>", 2035 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift); 2036 init->offset += 17; 2037 2038 data = init_shift(init_rd32(init, saddr), sshift) & smask; 2039 data = init_xlat_(init, index, data) << shift; 2040 init_mask(init, daddr, ~dmask, data); 2041 } 2042 2043 /** 2044 * INIT_ZM_MASK_ADD - opcode 0x97 2045 * 2046 */ 2047 static void 2048 init_zm_mask_add(struct nvbios_init *init) 2049 { 2050 struct nvkm_bios *bios = init->bios; 2051 u32 addr = nv_ro32(bios, init->offset + 1); 2052 u32 mask = nv_ro32(bios, init->offset + 5); 2053 u32 add = nv_ro32(bios, init->offset + 9); 2054 u32 data; 2055 2056 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); 2057 init->offset += 13; 2058 2059 data = init_rd32(init, addr); 2060 data = (data & mask) | ((data + add) & ~mask); 2061 init_wr32(init, addr, data); 2062 } 2063 2064 /** 2065 * INIT_AUXCH - opcode 0x98 2066 * 2067 */ 2068 static void 2069 init_auxch(struct nvbios_init *init) 2070 { 2071 struct nvkm_bios *bios = init->bios; 2072 u32 addr = nv_ro32(bios, init->offset + 1); 2073 u8 count = nv_ro08(bios, init->offset + 5); 2074 2075 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2076 init->offset += 6; 2077 2078 while (count--) { 2079 u8 mask = nv_ro08(bios, init->offset + 0); 2080 u8 data = nv_ro08(bios, init->offset + 1); 2081 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 2082 mask = init_rdauxr(init, addr) & mask; 2083 init_wrauxr(init, addr, mask | data); 2084 init->offset += 2; 2085 } 2086 } 2087 2088 /** 2089 * INIT_AUXCH - opcode 0x99 2090 * 2091 */ 2092 static void 2093 init_zm_auxch(struct nvbios_init *init) 2094 { 2095 struct nvkm_bios *bios = init->bios; 2096 u32 addr = nv_ro32(bios, init->offset + 1); 2097 u8 count = nv_ro08(bios, init->offset + 5); 2098 2099 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2100 init->offset += 6; 2101 2102 while (count--) { 2103 u8 data = nv_ro08(bios, init->offset + 0); 2104 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data); 2105 init_wrauxr(init, addr, data); 2106 init->offset += 1; 2107 } 2108 } 2109 2110 /** 2111 * INIT_I2C_LONG_IF - opcode 0x9a 2112 * 2113 */ 2114 static void 2115 init_i2c_long_if(struct nvbios_init *init) 2116 { 2117 struct nvkm_bios *bios = init->bios; 2118 u8 index = nv_ro08(bios, init->offset + 1); 2119 u8 addr = nv_ro08(bios, init->offset + 2) >> 1; 2120 u8 reglo = nv_ro08(bios, init->offset + 3); 2121 u8 reghi = nv_ro08(bios, init->offset + 4); 2122 u8 mask = nv_ro08(bios, init->offset + 5); 2123 u8 data = nv_ro08(bios, init->offset + 6); 2124 struct nvkm_i2c_port *port; 2125 2126 trace("I2C_LONG_IF\t" 2127 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n", 2128 index, addr, reglo, reghi, mask, data); 2129 init->offset += 7; 2130 2131 port = init_i2c(init, index); 2132 if (port) { 2133 u8 i[2] = { reghi, reglo }; 2134 u8 o[1] = {}; 2135 struct i2c_msg msg[] = { 2136 { .addr = addr, .flags = 0, .len = 2, .buf = i }, 2137 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o } 2138 }; 2139 int ret; 2140 2141 ret = i2c_transfer(&port->adapter, msg, 2); 2142 if (ret == 2 && ((o[0] & mask) == data)) 2143 return; 2144 } 2145 2146 init_exec_set(init, false); 2147 } 2148 2149 /** 2150 * INIT_GPIO_NE - opcode 0xa9 2151 * 2152 */ 2153 static void 2154 init_gpio_ne(struct nvbios_init *init) 2155 { 2156 struct nvkm_bios *bios = init->bios; 2157 struct nvkm_gpio *gpio = nvkm_gpio(bios); 2158 struct dcb_gpio_func func; 2159 u8 count = nv_ro08(bios, init->offset + 1); 2160 u8 idx = 0, ver, len; 2161 u16 data, i; 2162 2163 trace("GPIO_NE\t"); 2164 init->offset += 2; 2165 2166 for (i = init->offset; i < init->offset + count; i++) 2167 cont("0x%02x ", nv_ro08(bios, i)); 2168 cont("\n"); 2169 2170 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) { 2171 if (func.func != DCB_GPIO_UNUSED) { 2172 for (i = init->offset; i < init->offset + count; i++) { 2173 if (func.func == nv_ro08(bios, i)) 2174 break; 2175 } 2176 2177 trace("\tFUNC[0x%02x]", func.func); 2178 if (i == (init->offset + count)) { 2179 cont(" *"); 2180 if (init_exec(init) && gpio && gpio->reset) 2181 gpio->reset(gpio, func.func); 2182 } 2183 cont("\n"); 2184 } 2185 } 2186 2187 init->offset += count; 2188 } 2189 2190 static struct nvbios_init_opcode { 2191 void (*exec)(struct nvbios_init *); 2192 } init_opcode[] = { 2193 [0x32] = { init_io_restrict_prog }, 2194 [0x33] = { init_repeat }, 2195 [0x34] = { init_io_restrict_pll }, 2196 [0x36] = { init_end_repeat }, 2197 [0x37] = { init_copy }, 2198 [0x38] = { init_not }, 2199 [0x39] = { init_io_flag_condition }, 2200 [0x3a] = { init_dp_condition }, 2201 [0x3b] = { init_io_mask_or }, 2202 [0x3c] = { init_io_or }, 2203 [0x47] = { init_andn_reg }, 2204 [0x48] = { init_or_reg }, 2205 [0x49] = { init_idx_addr_latched }, 2206 [0x4a] = { init_io_restrict_pll2 }, 2207 [0x4b] = { init_pll2 }, 2208 [0x4c] = { init_i2c_byte }, 2209 [0x4d] = { init_zm_i2c_byte }, 2210 [0x4e] = { init_zm_i2c }, 2211 [0x4f] = { init_tmds }, 2212 [0x50] = { init_zm_tmds_group }, 2213 [0x51] = { init_cr_idx_adr_latch }, 2214 [0x52] = { init_cr }, 2215 [0x53] = { init_zm_cr }, 2216 [0x54] = { init_zm_cr_group }, 2217 [0x56] = { init_condition_time }, 2218 [0x57] = { init_ltime }, 2219 [0x58] = { init_zm_reg_sequence }, 2220 [0x59] = { init_pll_indirect }, 2221 [0x5a] = { init_zm_reg_indirect }, 2222 [0x5b] = { init_sub_direct }, 2223 [0x5c] = { init_jump }, 2224 [0x5e] = { init_i2c_if }, 2225 [0x5f] = { init_copy_nv_reg }, 2226 [0x62] = { init_zm_index_io }, 2227 [0x63] = { init_compute_mem }, 2228 [0x65] = { init_reset }, 2229 [0x66] = { init_configure_mem }, 2230 [0x67] = { init_configure_clk }, 2231 [0x68] = { init_configure_preinit }, 2232 [0x69] = { init_io }, 2233 [0x6b] = { init_sub }, 2234 [0x6d] = { init_ram_condition }, 2235 [0x6e] = { init_nv_reg }, 2236 [0x6f] = { init_macro }, 2237 [0x71] = { init_done }, 2238 [0x72] = { init_resume }, 2239 [0x73] = { init_strap_condition }, 2240 [0x74] = { init_time }, 2241 [0x75] = { init_condition }, 2242 [0x76] = { init_io_condition }, 2243 [0x77] = { init_zm_reg16 }, 2244 [0x78] = { init_index_io }, 2245 [0x79] = { init_pll }, 2246 [0x7a] = { init_zm_reg }, 2247 [0x87] = { init_ram_restrict_pll }, 2248 [0x8c] = { init_reserved }, 2249 [0x8d] = { init_reserved }, 2250 [0x8e] = { init_gpio }, 2251 [0x8f] = { init_ram_restrict_zm_reg_group }, 2252 [0x90] = { init_copy_zm_reg }, 2253 [0x91] = { init_zm_reg_group }, 2254 [0x92] = { init_reserved }, 2255 [0x96] = { init_xlat }, 2256 [0x97] = { init_zm_mask_add }, 2257 [0x98] = { init_auxch }, 2258 [0x99] = { init_zm_auxch }, 2259 [0x9a] = { init_i2c_long_if }, 2260 [0xa9] = { init_gpio_ne }, 2261 [0xaa] = { init_reserved }, 2262 }; 2263 2264 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0])) 2265 2266 int 2267 nvbios_exec(struct nvbios_init *init) 2268 { 2269 init->nested++; 2270 while (init->offset) { 2271 u8 opcode = nv_ro08(init->bios, init->offset); 2272 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) { 2273 error("unknown opcode 0x%02x\n", opcode); 2274 return -EINVAL; 2275 } 2276 2277 init_opcode[opcode].exec(init); 2278 } 2279 init->nested--; 2280 return 0; 2281 } 2282 2283 int 2284 nvbios_init(struct nvkm_subdev *subdev, bool execute) 2285 { 2286 struct nvkm_bios *bios = nvkm_bios(subdev); 2287 int ret = 0; 2288 int i = -1; 2289 u16 data; 2290 2291 if (execute) 2292 nv_info(bios, "running init tables\n"); 2293 while (!ret && (data = (init_script(bios, ++i)))) { 2294 struct nvbios_init init = { 2295 .subdev = subdev, 2296 .bios = bios, 2297 .offset = data, 2298 .outp = NULL, 2299 .crtc = -1, 2300 .execute = execute ? 1 : 0, 2301 }; 2302 2303 ret = nvbios_exec(&init); 2304 } 2305 2306 /* the vbios parser will run this right after the normal init 2307 * tables, whereas the binary driver appears to run it later. 2308 */ 2309 if (!ret && (data = init_unknown_script(bios))) { 2310 struct nvbios_init init = { 2311 .subdev = subdev, 2312 .bios = bios, 2313 .offset = data, 2314 .outp = NULL, 2315 .crtc = -1, 2316 .execute = execute ? 1 : 0, 2317 }; 2318 2319 ret = nvbios_exec(&init); 2320 } 2321 2322 return ret; 2323 } 2324