1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/bios.h> 25 #include <subdev/bios/bit.h> 26 #include <subdev/bios/bmp.h> 27 #include <subdev/bios/conn.h> 28 #include <subdev/bios/dcb.h> 29 #include <subdev/bios/dp.h> 30 #include <subdev/bios/gpio.h> 31 #include <subdev/bios/init.h> 32 #include <subdev/bios/ramcfg.h> 33 34 #include <subdev/devinit.h> 35 #include <subdev/gpio.h> 36 #include <subdev/i2c.h> 37 #include <subdev/vga.h> 38 39 #define bioslog(lvl, fmt, args...) do { \ 40 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \ 41 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \ 42 } while(0) 43 #define cont(fmt, args...) do { \ 44 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \ 45 printk(fmt, ##args); \ 46 } while(0) 47 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args) 48 #define warn(fmt, args...) bioslog(WARN, fmt, ##args) 49 #define error(fmt, args...) bioslog(ERROR, fmt, ##args) 50 51 /****************************************************************************** 52 * init parser control flow helpers 53 *****************************************************************************/ 54 55 static inline bool 56 init_exec(struct nvbios_init *init) 57 { 58 return (init->execute == 1) || ((init->execute & 5) == 5); 59 } 60 61 static inline void 62 init_exec_set(struct nvbios_init *init, bool exec) 63 { 64 if (exec) init->execute &= 0xfd; 65 else init->execute |= 0x02; 66 } 67 68 static inline void 69 init_exec_inv(struct nvbios_init *init) 70 { 71 init->execute ^= 0x02; 72 } 73 74 static inline void 75 init_exec_force(struct nvbios_init *init, bool exec) 76 { 77 if (exec) init->execute |= 0x04; 78 else init->execute &= 0xfb; 79 } 80 81 /****************************************************************************** 82 * init parser wrappers for normal register/i2c/whatever accessors 83 *****************************************************************************/ 84 85 static inline int 86 init_or(struct nvbios_init *init) 87 { 88 if (init_exec(init)) { 89 if (init->outp) 90 return ffs(init->outp->or) - 1; 91 error("script needs OR!!\n"); 92 } 93 return 0; 94 } 95 96 static inline int 97 init_link(struct nvbios_init *init) 98 { 99 if (init_exec(init)) { 100 if (init->outp) 101 return !(init->outp->sorconf.link & 1); 102 error("script needs OR link\n"); 103 } 104 return 0; 105 } 106 107 static inline int 108 init_crtc(struct nvbios_init *init) 109 { 110 if (init_exec(init)) { 111 if (init->crtc >= 0) 112 return init->crtc; 113 error("script needs crtc\n"); 114 } 115 return 0; 116 } 117 118 static u8 119 init_conn(struct nvbios_init *init) 120 { 121 struct nvkm_bios *bios = init->bios; 122 struct nvbios_connE connE; 123 u8 ver, hdr; 124 u32 conn; 125 126 if (init_exec(init)) { 127 if (init->outp) { 128 conn = init->outp->connector; 129 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE); 130 if (conn) 131 return connE.type; 132 } 133 134 error("script needs connector type\n"); 135 } 136 137 return 0xff; 138 } 139 140 static inline u32 141 init_nvreg(struct nvbios_init *init, u32 reg) 142 { 143 struct nvkm_devinit *devinit = nvkm_devinit(init->bios); 144 145 /* C51 (at least) sometimes has the lower bits set which the VBIOS 146 * interprets to mean that access needs to go through certain IO 147 * ports instead. The NVIDIA binary driver has been seen to access 148 * these through the NV register address, so lets assume we can 149 * do the same 150 */ 151 reg &= ~0x00000003; 152 153 /* GF8+ display scripts need register addresses mangled a bit to 154 * select a specific CRTC/OR 155 */ 156 if (nv_device(init->bios)->card_type >= NV_50) { 157 if (reg & 0x80000000) { 158 reg += init_crtc(init) * 0x800; 159 reg &= ~0x80000000; 160 } 161 162 if (reg & 0x40000000) { 163 reg += init_or(init) * 0x800; 164 reg &= ~0x40000000; 165 if (reg & 0x20000000) { 166 reg += init_link(init) * 0x80; 167 reg &= ~0x20000000; 168 } 169 } 170 } 171 172 if (reg & ~0x00fffffc) 173 warn("unknown bits in register 0x%08x\n", reg); 174 175 if (devinit->mmio) 176 reg = devinit->mmio(devinit, reg); 177 return reg; 178 } 179 180 static u32 181 init_rd32(struct nvbios_init *init, u32 reg) 182 { 183 struct nvkm_device *device = init->bios->subdev.device; 184 reg = init_nvreg(init, reg); 185 if (reg != ~0 && init_exec(init)) 186 return nvkm_rd32(device, reg); 187 return 0x00000000; 188 } 189 190 static void 191 init_wr32(struct nvbios_init *init, u32 reg, u32 val) 192 { 193 struct nvkm_device *device = init->bios->subdev.device; 194 reg = init_nvreg(init, reg); 195 if (reg != ~0 && init_exec(init)) 196 nvkm_wr32(device, reg, val); 197 } 198 199 static u32 200 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) 201 { 202 struct nvkm_device *device = init->bios->subdev.device; 203 reg = init_nvreg(init, reg); 204 if (reg != ~0 && init_exec(init)) { 205 u32 tmp = nvkm_rd32(device, reg); 206 nvkm_wr32(device, reg, (tmp & ~mask) | val); 207 return tmp; 208 } 209 return 0x00000000; 210 } 211 212 static u8 213 init_rdport(struct nvbios_init *init, u16 port) 214 { 215 if (init_exec(init)) 216 return nv_rdport(init->subdev, init->crtc, port); 217 return 0x00; 218 } 219 220 static void 221 init_wrport(struct nvbios_init *init, u16 port, u8 value) 222 { 223 if (init_exec(init)) 224 nv_wrport(init->subdev, init->crtc, port, value); 225 } 226 227 static u8 228 init_rdvgai(struct nvbios_init *init, u16 port, u8 index) 229 { 230 struct nvkm_subdev *subdev = init->subdev; 231 if (init_exec(init)) { 232 int head = init->crtc < 0 ? 0 : init->crtc; 233 return nv_rdvgai(subdev, head, port, index); 234 } 235 return 0x00; 236 } 237 238 static void 239 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value) 240 { 241 /* force head 0 for updates to cr44, it only exists on first head */ 242 if (nv_device(init->subdev)->card_type < NV_50) { 243 if (port == 0x03d4 && index == 0x44) 244 init->crtc = 0; 245 } 246 247 if (init_exec(init)) { 248 int head = init->crtc < 0 ? 0 : init->crtc; 249 nv_wrvgai(init->subdev, head, port, index, value); 250 } 251 252 /* select head 1 if cr44 write selected it */ 253 if (nv_device(init->subdev)->card_type < NV_50) { 254 if (port == 0x03d4 && index == 0x44 && value == 3) 255 init->crtc = 1; 256 } 257 } 258 259 static struct nvkm_i2c_port * 260 init_i2c(struct nvbios_init *init, int index) 261 { 262 struct nvkm_i2c *i2c = nvkm_i2c(init->bios); 263 264 if (index == 0xff) { 265 index = NV_I2C_DEFAULT(0); 266 if (init->outp && init->outp->i2c_upper_default) 267 index = NV_I2C_DEFAULT(1); 268 } else 269 if (index < 0) { 270 if (!init->outp) { 271 if (init_exec(init)) 272 error("script needs output for i2c\n"); 273 return NULL; 274 } 275 276 if (index == -2 && init->outp->location) { 277 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev); 278 return i2c->find_type(i2c, index); 279 } 280 281 index = init->outp->i2c_index; 282 if (init->outp->type == DCB_OUTPUT_DP) 283 index += NV_I2C_AUX(0); 284 } 285 286 return i2c->find(i2c, index); 287 } 288 289 static int 290 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) 291 { 292 struct nvkm_i2c_port *port = init_i2c(init, index); 293 if (port && init_exec(init)) 294 return nv_rdi2cr(port, addr, reg); 295 return -ENODEV; 296 } 297 298 static int 299 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) 300 { 301 struct nvkm_i2c_port *port = init_i2c(init, index); 302 if (port && init_exec(init)) 303 return nv_wri2cr(port, addr, reg, val); 304 return -ENODEV; 305 } 306 307 static u8 308 init_rdauxr(struct nvbios_init *init, u32 addr) 309 { 310 struct nvkm_i2c_port *port = init_i2c(init, -2); 311 u8 data; 312 313 if (port && init_exec(init)) { 314 int ret = nv_rdaux(port, addr, &data, 1); 315 if (ret == 0) 316 return data; 317 trace("auxch read failed with %d\n", ret); 318 } 319 320 return 0x00; 321 } 322 323 static int 324 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) 325 { 326 struct nvkm_i2c_port *port = init_i2c(init, -2); 327 if (port && init_exec(init)) { 328 int ret = nv_wraux(port, addr, &data, 1); 329 if (ret) 330 trace("auxch write failed with %d\n", ret); 331 return ret; 332 } 333 return -ENODEV; 334 } 335 336 static void 337 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) 338 { 339 struct nvkm_devinit *devinit = nvkm_devinit(init->bios); 340 if (devinit->pll_set && init_exec(init)) { 341 int ret = devinit->pll_set(devinit, id, freq); 342 if (ret) 343 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq); 344 } 345 } 346 347 /****************************************************************************** 348 * parsing of bios structures that are required to execute init tables 349 *****************************************************************************/ 350 351 static u16 352 init_table(struct nvkm_bios *bios, u16 *len) 353 { 354 struct bit_entry bit_I; 355 356 if (!bit_entry(bios, 'I', &bit_I)) { 357 *len = bit_I.length; 358 return bit_I.offset; 359 } 360 361 if (bmp_version(bios) >= 0x0510) { 362 *len = 14; 363 return bios->bmp_offset + 75; 364 } 365 366 return 0x0000; 367 } 368 369 static u16 370 init_table_(struct nvbios_init *init, u16 offset, const char *name) 371 { 372 struct nvkm_bios *bios = init->bios; 373 u16 len, data = init_table(bios, &len); 374 if (data) { 375 if (len >= offset + 2) { 376 data = nv_ro16(bios, data + offset); 377 if (data) 378 return data; 379 380 warn("%s pointer invalid\n", name); 381 return 0x0000; 382 } 383 384 warn("init data too short for %s pointer", name); 385 return 0x0000; 386 } 387 388 warn("init data not found\n"); 389 return 0x0000; 390 } 391 392 #define init_script_table(b) init_table_((b), 0x00, "script table") 393 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table") 394 #define init_macro_table(b) init_table_((b), 0x04, "macro table") 395 #define init_condition_table(b) init_table_((b), 0x06, "condition table") 396 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table") 397 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table") 398 #define init_function_table(b) init_table_((b), 0x0c, "function table") 399 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); 400 401 static u16 402 init_script(struct nvkm_bios *bios, int index) 403 { 404 struct nvbios_init init = { .bios = bios }; 405 u16 bmp_ver = bmp_version(bios), data; 406 407 if (bmp_ver && bmp_ver < 0x0510) { 408 if (index > 1 || bmp_ver < 0x0100) 409 return 0x0000; 410 411 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18); 412 return nv_ro16(bios, data + (index * 2)); 413 } 414 415 data = init_script_table(&init); 416 if (data) 417 return nv_ro16(bios, data + (index * 2)); 418 419 return 0x0000; 420 } 421 422 static u16 423 init_unknown_script(struct nvkm_bios *bios) 424 { 425 u16 len, data = init_table(bios, &len); 426 if (data && len >= 16) 427 return nv_ro16(bios, data + 14); 428 return 0x0000; 429 } 430 431 static u8 432 init_ram_restrict_group_count(struct nvbios_init *init) 433 { 434 return nvbios_ramcfg_count(init->bios); 435 } 436 437 static u8 438 init_ram_restrict(struct nvbios_init *init) 439 { 440 /* This appears to be the behaviour of the VBIOS parser, and *is* 441 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to 442 * avoid fucking up the memory controller (somehow) by reading it 443 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode. 444 * 445 * Preserving the non-caching behaviour on earlier chipsets just 446 * in case *not* re-reading the strap causes similar breakage. 447 */ 448 if (!init->ramcfg || init->bios->version.major < 0x70) 449 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev); 450 return (init->ramcfg & 0x7fffffff); 451 } 452 453 static u8 454 init_xlat_(struct nvbios_init *init, u8 index, u8 offset) 455 { 456 struct nvkm_bios *bios = init->bios; 457 u16 table = init_xlat_table(init); 458 if (table) { 459 u16 data = nv_ro16(bios, table + (index * 2)); 460 if (data) 461 return nv_ro08(bios, data + offset); 462 warn("xlat table pointer %d invalid\n", index); 463 } 464 return 0x00; 465 } 466 467 /****************************************************************************** 468 * utility functions used by various init opcode handlers 469 *****************************************************************************/ 470 471 static bool 472 init_condition_met(struct nvbios_init *init, u8 cond) 473 { 474 struct nvkm_bios *bios = init->bios; 475 u16 table = init_condition_table(init); 476 if (table) { 477 u32 reg = nv_ro32(bios, table + (cond * 12) + 0); 478 u32 msk = nv_ro32(bios, table + (cond * 12) + 4); 479 u32 val = nv_ro32(bios, table + (cond * 12) + 8); 480 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n", 481 cond, reg, msk, val); 482 return (init_rd32(init, reg) & msk) == val; 483 } 484 return false; 485 } 486 487 static bool 488 init_io_condition_met(struct nvbios_init *init, u8 cond) 489 { 490 struct nvkm_bios *bios = init->bios; 491 u16 table = init_io_condition_table(init); 492 if (table) { 493 u16 port = nv_ro16(bios, table + (cond * 5) + 0); 494 u8 index = nv_ro08(bios, table + (cond * 5) + 2); 495 u8 mask = nv_ro08(bios, table + (cond * 5) + 3); 496 u8 value = nv_ro08(bios, table + (cond * 5) + 4); 497 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n", 498 cond, port, index, mask, value); 499 return (init_rdvgai(init, port, index) & mask) == value; 500 } 501 return false; 502 } 503 504 static bool 505 init_io_flag_condition_met(struct nvbios_init *init, u8 cond) 506 { 507 struct nvkm_bios *bios = init->bios; 508 u16 table = init_io_flag_condition_table(init); 509 if (table) { 510 u16 port = nv_ro16(bios, table + (cond * 9) + 0); 511 u8 index = nv_ro08(bios, table + (cond * 9) + 2); 512 u8 mask = nv_ro08(bios, table + (cond * 9) + 3); 513 u8 shift = nv_ro08(bios, table + (cond * 9) + 4); 514 u16 data = nv_ro16(bios, table + (cond * 9) + 5); 515 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7); 516 u8 value = nv_ro08(bios, table + (cond * 9) + 8); 517 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift; 518 return (nv_ro08(bios, data + ioval) & dmask) == value; 519 } 520 return false; 521 } 522 523 static inline u32 524 init_shift(u32 data, u8 shift) 525 { 526 if (shift < 0x80) 527 return data >> shift; 528 return data << (0x100 - shift); 529 } 530 531 static u32 532 init_tmds_reg(struct nvbios_init *init, u8 tmds) 533 { 534 /* For mlv < 0x80, it is an index into a table of TMDS base addresses. 535 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 536 * CR58 for CR57 = 0 to index a table of offsets to the basic 537 * 0x6808b0 address. 538 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 539 * CR58 for CR57 = 0 to index a table of offsets to the basic 540 * 0x6808b0 address, and then flip the offset by 8. 541 */ 542 const int pramdac_offset[13] = { 543 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 544 const u32 pramdac_table[4] = { 545 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 546 547 if (tmds >= 0x80) { 548 if (init->outp) { 549 u32 dacoffset = pramdac_offset[init->outp->or]; 550 if (tmds == 0x81) 551 dacoffset ^= 8; 552 return 0x6808b0 + dacoffset; 553 } 554 555 if (init_exec(init)) 556 error("tmds opcodes need dcb\n"); 557 } else { 558 if (tmds < ARRAY_SIZE(pramdac_table)) 559 return pramdac_table[tmds]; 560 561 error("tmds selector 0x%02x unknown\n", tmds); 562 } 563 564 return 0; 565 } 566 567 /****************************************************************************** 568 * init opcode handlers 569 *****************************************************************************/ 570 571 /** 572 * init_reserved - stub for various unknown/unused single-byte opcodes 573 * 574 */ 575 static void 576 init_reserved(struct nvbios_init *init) 577 { 578 u8 opcode = nv_ro08(init->bios, init->offset); 579 u8 length, i; 580 581 switch (opcode) { 582 case 0xaa: 583 length = 4; 584 break; 585 default: 586 length = 1; 587 break; 588 } 589 590 trace("RESERVED 0x%02x\t", opcode); 591 for (i = 1; i < length; i++) 592 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i)); 593 cont("\n"); 594 init->offset += length; 595 } 596 597 /** 598 * INIT_DONE - opcode 0x71 599 * 600 */ 601 static void 602 init_done(struct nvbios_init *init) 603 { 604 trace("DONE\n"); 605 init->offset = 0x0000; 606 } 607 608 /** 609 * INIT_IO_RESTRICT_PROG - opcode 0x32 610 * 611 */ 612 static void 613 init_io_restrict_prog(struct nvbios_init *init) 614 { 615 struct nvkm_bios *bios = init->bios; 616 u16 port = nv_ro16(bios, init->offset + 1); 617 u8 index = nv_ro08(bios, init->offset + 3); 618 u8 mask = nv_ro08(bios, init->offset + 4); 619 u8 shift = nv_ro08(bios, init->offset + 5); 620 u8 count = nv_ro08(bios, init->offset + 6); 621 u32 reg = nv_ro32(bios, init->offset + 7); 622 u8 conf, i; 623 624 trace("IO_RESTRICT_PROG\tR[0x%06x] = " 625 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n", 626 reg, port, index, mask, shift); 627 init->offset += 11; 628 629 conf = (init_rdvgai(init, port, index) & mask) >> shift; 630 for (i = 0; i < count; i++) { 631 u32 data = nv_ro32(bios, init->offset); 632 633 if (i == conf) { 634 trace("\t0x%08x *\n", data); 635 init_wr32(init, reg, data); 636 } else { 637 trace("\t0x%08x\n", data); 638 } 639 640 init->offset += 4; 641 } 642 trace("}]\n"); 643 } 644 645 /** 646 * INIT_REPEAT - opcode 0x33 647 * 648 */ 649 static void 650 init_repeat(struct nvbios_init *init) 651 { 652 struct nvkm_bios *bios = init->bios; 653 u8 count = nv_ro08(bios, init->offset + 1); 654 u16 repeat = init->repeat; 655 656 trace("REPEAT\t0x%02x\n", count); 657 init->offset += 2; 658 659 init->repeat = init->offset; 660 init->repend = init->offset; 661 while (count--) { 662 init->offset = init->repeat; 663 nvbios_exec(init); 664 if (count) 665 trace("REPEAT\t0x%02x\n", count); 666 } 667 init->offset = init->repend; 668 init->repeat = repeat; 669 } 670 671 /** 672 * INIT_IO_RESTRICT_PLL - opcode 0x34 673 * 674 */ 675 static void 676 init_io_restrict_pll(struct nvbios_init *init) 677 { 678 struct nvkm_bios *bios = init->bios; 679 u16 port = nv_ro16(bios, init->offset + 1); 680 u8 index = nv_ro08(bios, init->offset + 3); 681 u8 mask = nv_ro08(bios, init->offset + 4); 682 u8 shift = nv_ro08(bios, init->offset + 5); 683 s8 iofc = nv_ro08(bios, init->offset + 6); 684 u8 count = nv_ro08(bios, init->offset + 7); 685 u32 reg = nv_ro32(bios, init->offset + 8); 686 u8 conf, i; 687 688 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= " 689 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n", 690 reg, port, index, mask, shift, iofc); 691 init->offset += 12; 692 693 conf = (init_rdvgai(init, port, index) & mask) >> shift; 694 for (i = 0; i < count; i++) { 695 u32 freq = nv_ro16(bios, init->offset) * 10; 696 697 if (i == conf) { 698 trace("\t%dkHz *\n", freq); 699 if (iofc > 0 && init_io_flag_condition_met(init, iofc)) 700 freq *= 2; 701 init_prog_pll(init, reg, freq); 702 } else { 703 trace("\t%dkHz\n", freq); 704 } 705 706 init->offset += 2; 707 } 708 trace("}]\n"); 709 } 710 711 /** 712 * INIT_END_REPEAT - opcode 0x36 713 * 714 */ 715 static void 716 init_end_repeat(struct nvbios_init *init) 717 { 718 trace("END_REPEAT\n"); 719 init->offset += 1; 720 721 if (init->repeat) { 722 init->repend = init->offset; 723 init->offset = 0; 724 } 725 } 726 727 /** 728 * INIT_COPY - opcode 0x37 729 * 730 */ 731 static void 732 init_copy(struct nvbios_init *init) 733 { 734 struct nvkm_bios *bios = init->bios; 735 u32 reg = nv_ro32(bios, init->offset + 1); 736 u8 shift = nv_ro08(bios, init->offset + 5); 737 u8 smask = nv_ro08(bios, init->offset + 6); 738 u16 port = nv_ro16(bios, init->offset + 7); 739 u8 index = nv_ro08(bios, init->offset + 9); 740 u8 mask = nv_ro08(bios, init->offset + 10); 741 u8 data; 742 743 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= " 744 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n", 745 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", 746 (shift & 0x80) ? (0x100 - shift) : shift, smask); 747 init->offset += 11; 748 749 data = init_rdvgai(init, port, index) & mask; 750 data |= init_shift(init_rd32(init, reg), shift) & smask; 751 init_wrvgai(init, port, index, data); 752 } 753 754 /** 755 * INIT_NOT - opcode 0x38 756 * 757 */ 758 static void 759 init_not(struct nvbios_init *init) 760 { 761 trace("NOT\n"); 762 init->offset += 1; 763 init_exec_inv(init); 764 } 765 766 /** 767 * INIT_IO_FLAG_CONDITION - opcode 0x39 768 * 769 */ 770 static void 771 init_io_flag_condition(struct nvbios_init *init) 772 { 773 struct nvkm_bios *bios = init->bios; 774 u8 cond = nv_ro08(bios, init->offset + 1); 775 776 trace("IO_FLAG_CONDITION\t0x%02x\n", cond); 777 init->offset += 2; 778 779 if (!init_io_flag_condition_met(init, cond)) 780 init_exec_set(init, false); 781 } 782 783 /** 784 * INIT_DP_CONDITION - opcode 0x3a 785 * 786 */ 787 static void 788 init_dp_condition(struct nvbios_init *init) 789 { 790 struct nvkm_bios *bios = init->bios; 791 struct nvbios_dpout info; 792 u8 cond = nv_ro08(bios, init->offset + 1); 793 u8 unkn = nv_ro08(bios, init->offset + 2); 794 u8 ver, hdr, cnt, len; 795 u16 data; 796 797 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn); 798 init->offset += 3; 799 800 switch (cond) { 801 case 0: 802 if (init_conn(init) != DCB_CONNECTOR_eDP) 803 init_exec_set(init, false); 804 break; 805 case 1: 806 case 2: 807 if ( init->outp && 808 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP, 809 (init->outp->or << 0) | 810 (init->outp->sorconf.link << 6), 811 &ver, &hdr, &cnt, &len, &info))) 812 { 813 if (!(info.flags & cond)) 814 init_exec_set(init, false); 815 break; 816 } 817 818 if (init_exec(init)) 819 warn("script needs dp output table data\n"); 820 break; 821 case 5: 822 if (!(init_rdauxr(init, 0x0d) & 1)) 823 init_exec_set(init, false); 824 break; 825 default: 826 warn("unknown dp condition 0x%02x\n", cond); 827 break; 828 } 829 } 830 831 /** 832 * INIT_IO_MASK_OR - opcode 0x3b 833 * 834 */ 835 static void 836 init_io_mask_or(struct nvbios_init *init) 837 { 838 struct nvkm_bios *bios = init->bios; 839 u8 index = nv_ro08(bios, init->offset + 1); 840 u8 or = init_or(init); 841 u8 data; 842 843 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or); 844 init->offset += 2; 845 846 data = init_rdvgai(init, 0x03d4, index); 847 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); 848 } 849 850 /** 851 * INIT_IO_OR - opcode 0x3c 852 * 853 */ 854 static void 855 init_io_or(struct nvbios_init *init) 856 { 857 struct nvkm_bios *bios = init->bios; 858 u8 index = nv_ro08(bios, init->offset + 1); 859 u8 or = init_or(init); 860 u8 data; 861 862 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or); 863 init->offset += 2; 864 865 data = init_rdvgai(init, 0x03d4, index); 866 init_wrvgai(init, 0x03d4, index, data | (1 << or)); 867 } 868 869 /** 870 * INIT_ANDN_REG - opcode 0x47 871 * 872 */ 873 static void 874 init_andn_reg(struct nvbios_init *init) 875 { 876 struct nvkm_bios *bios = init->bios; 877 u32 reg = nv_ro32(bios, init->offset + 1); 878 u32 mask = nv_ro32(bios, init->offset + 5); 879 880 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask); 881 init->offset += 9; 882 883 init_mask(init, reg, mask, 0); 884 } 885 886 /** 887 * INIT_OR_REG - opcode 0x48 888 * 889 */ 890 static void 891 init_or_reg(struct nvbios_init *init) 892 { 893 struct nvkm_bios *bios = init->bios; 894 u32 reg = nv_ro32(bios, init->offset + 1); 895 u32 mask = nv_ro32(bios, init->offset + 5); 896 897 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask); 898 init->offset += 9; 899 900 init_mask(init, reg, 0, mask); 901 } 902 903 /** 904 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49 905 * 906 */ 907 static void 908 init_idx_addr_latched(struct nvbios_init *init) 909 { 910 struct nvkm_bios *bios = init->bios; 911 u32 creg = nv_ro32(bios, init->offset + 1); 912 u32 dreg = nv_ro32(bios, init->offset + 5); 913 u32 mask = nv_ro32(bios, init->offset + 9); 914 u32 data = nv_ro32(bios, init->offset + 13); 915 u8 count = nv_ro08(bios, init->offset + 17); 916 917 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg); 918 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data); 919 init->offset += 18; 920 921 while (count--) { 922 u8 iaddr = nv_ro08(bios, init->offset + 0); 923 u8 idata = nv_ro08(bios, init->offset + 1); 924 925 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata); 926 init->offset += 2; 927 928 init_wr32(init, dreg, idata); 929 init_mask(init, creg, ~mask, data | iaddr); 930 } 931 } 932 933 /** 934 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a 935 * 936 */ 937 static void 938 init_io_restrict_pll2(struct nvbios_init *init) 939 { 940 struct nvkm_bios *bios = init->bios; 941 u16 port = nv_ro16(bios, init->offset + 1); 942 u8 index = nv_ro08(bios, init->offset + 3); 943 u8 mask = nv_ro08(bios, init->offset + 4); 944 u8 shift = nv_ro08(bios, init->offset + 5); 945 u8 count = nv_ro08(bios, init->offset + 6); 946 u32 reg = nv_ro32(bios, init->offset + 7); 947 u8 conf, i; 948 949 trace("IO_RESTRICT_PLL2\t" 950 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n", 951 reg, port, index, mask, shift); 952 init->offset += 11; 953 954 conf = (init_rdvgai(init, port, index) & mask) >> shift; 955 for (i = 0; i < count; i++) { 956 u32 freq = nv_ro32(bios, init->offset); 957 if (i == conf) { 958 trace("\t%dkHz *\n", freq); 959 init_prog_pll(init, reg, freq); 960 } else { 961 trace("\t%dkHz\n", freq); 962 } 963 init->offset += 4; 964 } 965 trace("}]\n"); 966 } 967 968 /** 969 * INIT_PLL2 - opcode 0x4b 970 * 971 */ 972 static void 973 init_pll2(struct nvbios_init *init) 974 { 975 struct nvkm_bios *bios = init->bios; 976 u32 reg = nv_ro32(bios, init->offset + 1); 977 u32 freq = nv_ro32(bios, init->offset + 5); 978 979 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 980 init->offset += 9; 981 982 init_prog_pll(init, reg, freq); 983 } 984 985 /** 986 * INIT_I2C_BYTE - opcode 0x4c 987 * 988 */ 989 static void 990 init_i2c_byte(struct nvbios_init *init) 991 { 992 struct nvkm_bios *bios = init->bios; 993 u8 index = nv_ro08(bios, init->offset + 1); 994 u8 addr = nv_ro08(bios, init->offset + 2) >> 1; 995 u8 count = nv_ro08(bios, init->offset + 3); 996 997 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 998 init->offset += 4; 999 1000 while (count--) { 1001 u8 reg = nv_ro08(bios, init->offset + 0); 1002 u8 mask = nv_ro08(bios, init->offset + 1); 1003 u8 data = nv_ro08(bios, init->offset + 2); 1004 int val; 1005 1006 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); 1007 init->offset += 3; 1008 1009 val = init_rdi2cr(init, index, addr, reg); 1010 if (val < 0) 1011 continue; 1012 init_wri2cr(init, index, addr, reg, (val & mask) | data); 1013 } 1014 } 1015 1016 /** 1017 * INIT_ZM_I2C_BYTE - opcode 0x4d 1018 * 1019 */ 1020 static void 1021 init_zm_i2c_byte(struct nvbios_init *init) 1022 { 1023 struct nvkm_bios *bios = init->bios; 1024 u8 index = nv_ro08(bios, init->offset + 1); 1025 u8 addr = nv_ro08(bios, init->offset + 2) >> 1; 1026 u8 count = nv_ro08(bios, init->offset + 3); 1027 1028 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 1029 init->offset += 4; 1030 1031 while (count--) { 1032 u8 reg = nv_ro08(bios, init->offset + 0); 1033 u8 data = nv_ro08(bios, init->offset + 1); 1034 1035 trace("\t[0x%02x] = 0x%02x\n", reg, data); 1036 init->offset += 2; 1037 1038 init_wri2cr(init, index, addr, reg, data); 1039 } 1040 } 1041 1042 /** 1043 * INIT_ZM_I2C - opcode 0x4e 1044 * 1045 */ 1046 static void 1047 init_zm_i2c(struct nvbios_init *init) 1048 { 1049 struct nvkm_bios *bios = init->bios; 1050 u8 index = nv_ro08(bios, init->offset + 1); 1051 u8 addr = nv_ro08(bios, init->offset + 2) >> 1; 1052 u8 count = nv_ro08(bios, init->offset + 3); 1053 u8 data[256], i; 1054 1055 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr); 1056 init->offset += 4; 1057 1058 for (i = 0; i < count; i++) { 1059 data[i] = nv_ro08(bios, init->offset); 1060 trace("\t0x%02x\n", data[i]); 1061 init->offset++; 1062 } 1063 1064 if (init_exec(init)) { 1065 struct nvkm_i2c_port *port = init_i2c(init, index); 1066 struct i2c_msg msg = { 1067 .addr = addr, .flags = 0, .len = count, .buf = data, 1068 }; 1069 int ret; 1070 1071 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1) 1072 warn("i2c wr failed, %d\n", ret); 1073 } 1074 } 1075 1076 /** 1077 * INIT_TMDS - opcode 0x4f 1078 * 1079 */ 1080 static void 1081 init_tmds(struct nvbios_init *init) 1082 { 1083 struct nvkm_bios *bios = init->bios; 1084 u8 tmds = nv_ro08(bios, init->offset + 1); 1085 u8 addr = nv_ro08(bios, init->offset + 2); 1086 u8 mask = nv_ro08(bios, init->offset + 3); 1087 u8 data = nv_ro08(bios, init->offset + 4); 1088 u32 reg = init_tmds_reg(init, tmds); 1089 1090 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n", 1091 tmds, addr, mask, data); 1092 init->offset += 5; 1093 1094 if (reg == 0) 1095 return; 1096 1097 init_wr32(init, reg + 0, addr | 0x00010000); 1098 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); 1099 init_wr32(init, reg + 0, addr); 1100 } 1101 1102 /** 1103 * INIT_ZM_TMDS_GROUP - opcode 0x50 1104 * 1105 */ 1106 static void 1107 init_zm_tmds_group(struct nvbios_init *init) 1108 { 1109 struct nvkm_bios *bios = init->bios; 1110 u8 tmds = nv_ro08(bios, init->offset + 1); 1111 u8 count = nv_ro08(bios, init->offset + 2); 1112 u32 reg = init_tmds_reg(init, tmds); 1113 1114 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds); 1115 init->offset += 3; 1116 1117 while (count--) { 1118 u8 addr = nv_ro08(bios, init->offset + 0); 1119 u8 data = nv_ro08(bios, init->offset + 1); 1120 1121 trace("\t[0x%02x] = 0x%02x\n", addr, data); 1122 init->offset += 2; 1123 1124 init_wr32(init, reg + 4, data); 1125 init_wr32(init, reg + 0, addr); 1126 } 1127 } 1128 1129 /** 1130 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51 1131 * 1132 */ 1133 static void 1134 init_cr_idx_adr_latch(struct nvbios_init *init) 1135 { 1136 struct nvkm_bios *bios = init->bios; 1137 u8 addr0 = nv_ro08(bios, init->offset + 1); 1138 u8 addr1 = nv_ro08(bios, init->offset + 2); 1139 u8 base = nv_ro08(bios, init->offset + 3); 1140 u8 count = nv_ro08(bios, init->offset + 4); 1141 u8 save0; 1142 1143 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1); 1144 init->offset += 5; 1145 1146 save0 = init_rdvgai(init, 0x03d4, addr0); 1147 while (count--) { 1148 u8 data = nv_ro08(bios, init->offset); 1149 1150 trace("\t\t[0x%02x] = 0x%02x\n", base, data); 1151 init->offset += 1; 1152 1153 init_wrvgai(init, 0x03d4, addr0, base++); 1154 init_wrvgai(init, 0x03d4, addr1, data); 1155 } 1156 init_wrvgai(init, 0x03d4, addr0, save0); 1157 } 1158 1159 /** 1160 * INIT_CR - opcode 0x52 1161 * 1162 */ 1163 static void 1164 init_cr(struct nvbios_init *init) 1165 { 1166 struct nvkm_bios *bios = init->bios; 1167 u8 addr = nv_ro08(bios, init->offset + 1); 1168 u8 mask = nv_ro08(bios, init->offset + 2); 1169 u8 data = nv_ro08(bios, init->offset + 3); 1170 u8 val; 1171 1172 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 1173 init->offset += 4; 1174 1175 val = init_rdvgai(init, 0x03d4, addr) & mask; 1176 init_wrvgai(init, 0x03d4, addr, val | data); 1177 } 1178 1179 /** 1180 * INIT_ZM_CR - opcode 0x53 1181 * 1182 */ 1183 static void 1184 init_zm_cr(struct nvbios_init *init) 1185 { 1186 struct nvkm_bios *bios = init->bios; 1187 u8 addr = nv_ro08(bios, init->offset + 1); 1188 u8 data = nv_ro08(bios, init->offset + 2); 1189 1190 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data); 1191 init->offset += 3; 1192 1193 init_wrvgai(init, 0x03d4, addr, data); 1194 } 1195 1196 /** 1197 * INIT_ZM_CR_GROUP - opcode 0x54 1198 * 1199 */ 1200 static void 1201 init_zm_cr_group(struct nvbios_init *init) 1202 { 1203 struct nvkm_bios *bios = init->bios; 1204 u8 count = nv_ro08(bios, init->offset + 1); 1205 1206 trace("ZM_CR_GROUP\n"); 1207 init->offset += 2; 1208 1209 while (count--) { 1210 u8 addr = nv_ro08(bios, init->offset + 0); 1211 u8 data = nv_ro08(bios, init->offset + 1); 1212 1213 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data); 1214 init->offset += 2; 1215 1216 init_wrvgai(init, 0x03d4, addr, data); 1217 } 1218 } 1219 1220 /** 1221 * INIT_CONDITION_TIME - opcode 0x56 1222 * 1223 */ 1224 static void 1225 init_condition_time(struct nvbios_init *init) 1226 { 1227 struct nvkm_bios *bios = init->bios; 1228 u8 cond = nv_ro08(bios, init->offset + 1); 1229 u8 retry = nv_ro08(bios, init->offset + 2); 1230 u8 wait = min((u16)retry * 50, 100); 1231 1232 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry); 1233 init->offset += 3; 1234 1235 if (!init_exec(init)) 1236 return; 1237 1238 while (wait--) { 1239 if (init_condition_met(init, cond)) 1240 return; 1241 mdelay(20); 1242 } 1243 1244 init_exec_set(init, false); 1245 } 1246 1247 /** 1248 * INIT_LTIME - opcode 0x57 1249 * 1250 */ 1251 static void 1252 init_ltime(struct nvbios_init *init) 1253 { 1254 struct nvkm_bios *bios = init->bios; 1255 u16 msec = nv_ro16(bios, init->offset + 1); 1256 1257 trace("LTIME\t0x%04x\n", msec); 1258 init->offset += 3; 1259 1260 if (init_exec(init)) 1261 mdelay(msec); 1262 } 1263 1264 /** 1265 * INIT_ZM_REG_SEQUENCE - opcode 0x58 1266 * 1267 */ 1268 static void 1269 init_zm_reg_sequence(struct nvbios_init *init) 1270 { 1271 struct nvkm_bios *bios = init->bios; 1272 u32 base = nv_ro32(bios, init->offset + 1); 1273 u8 count = nv_ro08(bios, init->offset + 5); 1274 1275 trace("ZM_REG_SEQUENCE\t0x%02x\n", count); 1276 init->offset += 6; 1277 1278 while (count--) { 1279 u32 data = nv_ro32(bios, init->offset); 1280 1281 trace("\t\tR[0x%06x] = 0x%08x\n", base, data); 1282 init->offset += 4; 1283 1284 init_wr32(init, base, data); 1285 base += 4; 1286 } 1287 } 1288 1289 /** 1290 * INIT_PLL_INDIRECT - opcode 0x59 1291 * 1292 */ 1293 static void 1294 init_pll_indirect(struct nvbios_init *init) 1295 { 1296 struct nvkm_bios *bios = init->bios; 1297 u32 reg = nv_ro32(bios, init->offset + 1); 1298 u16 addr = nv_ro16(bios, init->offset + 5); 1299 u32 freq = (u32)nv_ro16(bios, addr) * 1000; 1300 1301 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n", 1302 reg, addr, freq); 1303 init->offset += 7; 1304 1305 init_prog_pll(init, reg, freq); 1306 } 1307 1308 /** 1309 * INIT_ZM_REG_INDIRECT - opcode 0x5a 1310 * 1311 */ 1312 static void 1313 init_zm_reg_indirect(struct nvbios_init *init) 1314 { 1315 struct nvkm_bios *bios = init->bios; 1316 u32 reg = nv_ro32(bios, init->offset + 1); 1317 u16 addr = nv_ro16(bios, init->offset + 5); 1318 u32 data = nv_ro32(bios, addr); 1319 1320 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n", 1321 reg, addr, data); 1322 init->offset += 7; 1323 1324 init_wr32(init, addr, data); 1325 } 1326 1327 /** 1328 * INIT_SUB_DIRECT - opcode 0x5b 1329 * 1330 */ 1331 static void 1332 init_sub_direct(struct nvbios_init *init) 1333 { 1334 struct nvkm_bios *bios = init->bios; 1335 u16 addr = nv_ro16(bios, init->offset + 1); 1336 u16 save; 1337 1338 trace("SUB_DIRECT\t0x%04x\n", addr); 1339 1340 if (init_exec(init)) { 1341 save = init->offset; 1342 init->offset = addr; 1343 if (nvbios_exec(init)) { 1344 error("error parsing sub-table\n"); 1345 return; 1346 } 1347 init->offset = save; 1348 } 1349 1350 init->offset += 3; 1351 } 1352 1353 /** 1354 * INIT_JUMP - opcode 0x5c 1355 * 1356 */ 1357 static void 1358 init_jump(struct nvbios_init *init) 1359 { 1360 struct nvkm_bios *bios = init->bios; 1361 u16 offset = nv_ro16(bios, init->offset + 1); 1362 1363 trace("JUMP\t0x%04x\n", offset); 1364 1365 if (init_exec(init)) 1366 init->offset = offset; 1367 else 1368 init->offset += 3; 1369 } 1370 1371 /** 1372 * INIT_I2C_IF - opcode 0x5e 1373 * 1374 */ 1375 static void 1376 init_i2c_if(struct nvbios_init *init) 1377 { 1378 struct nvkm_bios *bios = init->bios; 1379 u8 index = nv_ro08(bios, init->offset + 1); 1380 u8 addr = nv_ro08(bios, init->offset + 2); 1381 u8 reg = nv_ro08(bios, init->offset + 3); 1382 u8 mask = nv_ro08(bios, init->offset + 4); 1383 u8 data = nv_ro08(bios, init->offset + 5); 1384 u8 value; 1385 1386 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n", 1387 index, addr, reg, mask, data); 1388 init->offset += 6; 1389 init_exec_force(init, true); 1390 1391 value = init_rdi2cr(init, index, addr, reg); 1392 if ((value & mask) != data) 1393 init_exec_set(init, false); 1394 1395 init_exec_force(init, false); 1396 } 1397 1398 /** 1399 * INIT_COPY_NV_REG - opcode 0x5f 1400 * 1401 */ 1402 static void 1403 init_copy_nv_reg(struct nvbios_init *init) 1404 { 1405 struct nvkm_bios *bios = init->bios; 1406 u32 sreg = nv_ro32(bios, init->offset + 1); 1407 u8 shift = nv_ro08(bios, init->offset + 5); 1408 u32 smask = nv_ro32(bios, init->offset + 6); 1409 u32 sxor = nv_ro32(bios, init->offset + 10); 1410 u32 dreg = nv_ro32(bios, init->offset + 14); 1411 u32 dmask = nv_ro32(bios, init->offset + 18); 1412 u32 data; 1413 1414 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= " 1415 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n", 1416 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>", 1417 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor); 1418 init->offset += 22; 1419 1420 data = init_shift(init_rd32(init, sreg), shift); 1421 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor); 1422 } 1423 1424 /** 1425 * INIT_ZM_INDEX_IO - opcode 0x62 1426 * 1427 */ 1428 static void 1429 init_zm_index_io(struct nvbios_init *init) 1430 { 1431 struct nvkm_bios *bios = init->bios; 1432 u16 port = nv_ro16(bios, init->offset + 1); 1433 u8 index = nv_ro08(bios, init->offset + 3); 1434 u8 data = nv_ro08(bios, init->offset + 4); 1435 1436 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data); 1437 init->offset += 5; 1438 1439 init_wrvgai(init, port, index, data); 1440 } 1441 1442 /** 1443 * INIT_COMPUTE_MEM - opcode 0x63 1444 * 1445 */ 1446 static void 1447 init_compute_mem(struct nvbios_init *init) 1448 { 1449 struct nvkm_devinit *devinit = nvkm_devinit(init->bios); 1450 1451 trace("COMPUTE_MEM\n"); 1452 init->offset += 1; 1453 1454 init_exec_force(init, true); 1455 if (init_exec(init) && devinit->meminit) 1456 devinit->meminit(devinit); 1457 init_exec_force(init, false); 1458 } 1459 1460 /** 1461 * INIT_RESET - opcode 0x65 1462 * 1463 */ 1464 static void 1465 init_reset(struct nvbios_init *init) 1466 { 1467 struct nvkm_bios *bios = init->bios; 1468 u32 reg = nv_ro32(bios, init->offset + 1); 1469 u32 data1 = nv_ro32(bios, init->offset + 5); 1470 u32 data2 = nv_ro32(bios, init->offset + 9); 1471 u32 savepci19; 1472 1473 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2); 1474 init->offset += 13; 1475 init_exec_force(init, true); 1476 1477 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000); 1478 init_wr32(init, reg, data1); 1479 udelay(10); 1480 init_wr32(init, reg, data2); 1481 init_wr32(init, 0x00184c, savepci19); 1482 init_mask(init, 0x001850, 0x00000001, 0x00000000); 1483 1484 init_exec_force(init, false); 1485 } 1486 1487 /** 1488 * INIT_CONFIGURE_MEM - opcode 0x66 1489 * 1490 */ 1491 static u16 1492 init_configure_mem_clk(struct nvbios_init *init) 1493 { 1494 u16 mdata = bmp_mem_init_table(init->bios); 1495 if (mdata) 1496 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66; 1497 return mdata; 1498 } 1499 1500 static void 1501 init_configure_mem(struct nvbios_init *init) 1502 { 1503 struct nvkm_bios *bios = init->bios; 1504 u16 mdata, sdata; 1505 u32 addr, data; 1506 1507 trace("CONFIGURE_MEM\n"); 1508 init->offset += 1; 1509 1510 if (bios->version.major > 2) { 1511 init_done(init); 1512 return; 1513 } 1514 init_exec_force(init, true); 1515 1516 mdata = init_configure_mem_clk(init); 1517 sdata = bmp_sdr_seq_table(bios); 1518 if (nv_ro08(bios, mdata) & 0x01) 1519 sdata = bmp_ddr_seq_table(bios); 1520 mdata += 6; /* skip to data */ 1521 1522 data = init_rdvgai(init, 0x03c4, 0x01); 1523 init_wrvgai(init, 0x03c4, 0x01, data | 0x20); 1524 1525 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) { 1526 switch (addr) { 1527 case 0x10021c: /* CKE_NORMAL */ 1528 case 0x1002d0: /* CMD_REFRESH */ 1529 case 0x1002d4: /* CMD_PRECHARGE */ 1530 data = 0x00000001; 1531 break; 1532 default: 1533 data = nv_ro32(bios, mdata); 1534 mdata += 4; 1535 if (data == 0xffffffff) 1536 continue; 1537 break; 1538 } 1539 1540 init_wr32(init, addr, data); 1541 } 1542 1543 init_exec_force(init, false); 1544 } 1545 1546 /** 1547 * INIT_CONFIGURE_CLK - opcode 0x67 1548 * 1549 */ 1550 static void 1551 init_configure_clk(struct nvbios_init *init) 1552 { 1553 struct nvkm_bios *bios = init->bios; 1554 u16 mdata, clock; 1555 1556 trace("CONFIGURE_CLK\n"); 1557 init->offset += 1; 1558 1559 if (bios->version.major > 2) { 1560 init_done(init); 1561 return; 1562 } 1563 init_exec_force(init, true); 1564 1565 mdata = init_configure_mem_clk(init); 1566 1567 /* NVPLL */ 1568 clock = nv_ro16(bios, mdata + 4) * 10; 1569 init_prog_pll(init, 0x680500, clock); 1570 1571 /* MPLL */ 1572 clock = nv_ro16(bios, mdata + 2) * 10; 1573 if (nv_ro08(bios, mdata) & 0x01) 1574 clock *= 2; 1575 init_prog_pll(init, 0x680504, clock); 1576 1577 init_exec_force(init, false); 1578 } 1579 1580 /** 1581 * INIT_CONFIGURE_PREINIT - opcode 0x68 1582 * 1583 */ 1584 static void 1585 init_configure_preinit(struct nvbios_init *init) 1586 { 1587 struct nvkm_bios *bios = init->bios; 1588 u32 strap; 1589 1590 trace("CONFIGURE_PREINIT\n"); 1591 init->offset += 1; 1592 1593 if (bios->version.major > 2) { 1594 init_done(init); 1595 return; 1596 } 1597 init_exec_force(init, true); 1598 1599 strap = init_rd32(init, 0x101000); 1600 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6); 1601 init_wrvgai(init, 0x03d4, 0x3c, strap); 1602 1603 init_exec_force(init, false); 1604 } 1605 1606 /** 1607 * INIT_IO - opcode 0x69 1608 * 1609 */ 1610 static void 1611 init_io(struct nvbios_init *init) 1612 { 1613 struct nvkm_bios *bios = init->bios; 1614 u16 port = nv_ro16(bios, init->offset + 1); 1615 u8 mask = nv_ro16(bios, init->offset + 3); 1616 u8 data = nv_ro16(bios, init->offset + 4); 1617 u8 value; 1618 1619 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data); 1620 init->offset += 5; 1621 1622 /* ummm.. yes.. should really figure out wtf this is and why it's 1623 * needed some day.. it's almost certainly wrong, but, it also 1624 * somehow makes things work... 1625 */ 1626 if (nv_device(init->bios)->card_type >= NV_50 && 1627 port == 0x03c3 && data == 0x01) { 1628 init_mask(init, 0x614100, 0xf0800000, 0x00800000); 1629 init_mask(init, 0x00e18c, 0x00020000, 0x00020000); 1630 init_mask(init, 0x614900, 0xf0800000, 0x00800000); 1631 init_mask(init, 0x000200, 0x40000000, 0x00000000); 1632 mdelay(10); 1633 init_mask(init, 0x00e18c, 0x00020000, 0x00000000); 1634 init_mask(init, 0x000200, 0x40000000, 0x40000000); 1635 init_wr32(init, 0x614100, 0x00800018); 1636 init_wr32(init, 0x614900, 0x00800018); 1637 mdelay(10); 1638 init_wr32(init, 0x614100, 0x10000018); 1639 init_wr32(init, 0x614900, 0x10000018); 1640 } 1641 1642 value = init_rdport(init, port) & mask; 1643 init_wrport(init, port, data | value); 1644 } 1645 1646 /** 1647 * INIT_SUB - opcode 0x6b 1648 * 1649 */ 1650 static void 1651 init_sub(struct nvbios_init *init) 1652 { 1653 struct nvkm_bios *bios = init->bios; 1654 u8 index = nv_ro08(bios, init->offset + 1); 1655 u16 addr, save; 1656 1657 trace("SUB\t0x%02x\n", index); 1658 1659 addr = init_script(bios, index); 1660 if (addr && init_exec(init)) { 1661 save = init->offset; 1662 init->offset = addr; 1663 if (nvbios_exec(init)) { 1664 error("error parsing sub-table\n"); 1665 return; 1666 } 1667 init->offset = save; 1668 } 1669 1670 init->offset += 2; 1671 } 1672 1673 /** 1674 * INIT_RAM_CONDITION - opcode 0x6d 1675 * 1676 */ 1677 static void 1678 init_ram_condition(struct nvbios_init *init) 1679 { 1680 struct nvkm_bios *bios = init->bios; 1681 u8 mask = nv_ro08(bios, init->offset + 1); 1682 u8 value = nv_ro08(bios, init->offset + 2); 1683 1684 trace("RAM_CONDITION\t" 1685 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value); 1686 init->offset += 3; 1687 1688 if ((init_rd32(init, 0x100000) & mask) != value) 1689 init_exec_set(init, false); 1690 } 1691 1692 /** 1693 * INIT_NV_REG - opcode 0x6e 1694 * 1695 */ 1696 static void 1697 init_nv_reg(struct nvbios_init *init) 1698 { 1699 struct nvkm_bios *bios = init->bios; 1700 u32 reg = nv_ro32(bios, init->offset + 1); 1701 u32 mask = nv_ro32(bios, init->offset + 5); 1702 u32 data = nv_ro32(bios, init->offset + 9); 1703 1704 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); 1705 init->offset += 13; 1706 1707 init_mask(init, reg, ~mask, data); 1708 } 1709 1710 /** 1711 * INIT_MACRO - opcode 0x6f 1712 * 1713 */ 1714 static void 1715 init_macro(struct nvbios_init *init) 1716 { 1717 struct nvkm_bios *bios = init->bios; 1718 u8 macro = nv_ro08(bios, init->offset + 1); 1719 u16 table; 1720 1721 trace("MACRO\t0x%02x\n", macro); 1722 1723 table = init_macro_table(init); 1724 if (table) { 1725 u32 addr = nv_ro32(bios, table + (macro * 8) + 0); 1726 u32 data = nv_ro32(bios, table + (macro * 8) + 4); 1727 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data); 1728 init_wr32(init, addr, data); 1729 } 1730 1731 init->offset += 2; 1732 } 1733 1734 /** 1735 * INIT_RESUME - opcode 0x72 1736 * 1737 */ 1738 static void 1739 init_resume(struct nvbios_init *init) 1740 { 1741 trace("RESUME\n"); 1742 init->offset += 1; 1743 init_exec_set(init, true); 1744 } 1745 1746 /** 1747 * INIT_STRAP_CONDITION - opcode 0x73 1748 * 1749 */ 1750 static void 1751 init_strap_condition(struct nvbios_init *init) 1752 { 1753 struct nvkm_bios *bios = init->bios; 1754 u32 mask = nv_ro32(bios, init->offset + 1); 1755 u32 value = nv_ro32(bios, init->offset + 5); 1756 1757 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value); 1758 init->offset += 9; 1759 1760 if ((init_rd32(init, 0x101000) & mask) != value) 1761 init_exec_set(init, false); 1762 } 1763 1764 /** 1765 * INIT_TIME - opcode 0x74 1766 * 1767 */ 1768 static void 1769 init_time(struct nvbios_init *init) 1770 { 1771 struct nvkm_bios *bios = init->bios; 1772 u16 usec = nv_ro16(bios, init->offset + 1); 1773 1774 trace("TIME\t0x%04x\n", usec); 1775 init->offset += 3; 1776 1777 if (init_exec(init)) { 1778 if (usec < 1000) 1779 udelay(usec); 1780 else 1781 mdelay((usec + 900) / 1000); 1782 } 1783 } 1784 1785 /** 1786 * INIT_CONDITION - opcode 0x75 1787 * 1788 */ 1789 static void 1790 init_condition(struct nvbios_init *init) 1791 { 1792 struct nvkm_bios *bios = init->bios; 1793 u8 cond = nv_ro08(bios, init->offset + 1); 1794 1795 trace("CONDITION\t0x%02x\n", cond); 1796 init->offset += 2; 1797 1798 if (!init_condition_met(init, cond)) 1799 init_exec_set(init, false); 1800 } 1801 1802 /** 1803 * INIT_IO_CONDITION - opcode 0x76 1804 * 1805 */ 1806 static void 1807 init_io_condition(struct nvbios_init *init) 1808 { 1809 struct nvkm_bios *bios = init->bios; 1810 u8 cond = nv_ro08(bios, init->offset + 1); 1811 1812 trace("IO_CONDITION\t0x%02x\n", cond); 1813 init->offset += 2; 1814 1815 if (!init_io_condition_met(init, cond)) 1816 init_exec_set(init, false); 1817 } 1818 1819 /** 1820 * INIT_ZM_REG16 - opcode 0x77 1821 * 1822 */ 1823 static void 1824 init_zm_reg16(struct nvbios_init *init) 1825 { 1826 struct nvkm_bios *bios = init->bios; 1827 u32 addr = nv_ro32(bios, init->offset + 1); 1828 u16 data = nv_ro16(bios, init->offset + 5); 1829 1830 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data); 1831 init->offset += 7; 1832 1833 init_wr32(init, addr, data); 1834 } 1835 1836 /** 1837 * INIT_INDEX_IO - opcode 0x78 1838 * 1839 */ 1840 static void 1841 init_index_io(struct nvbios_init *init) 1842 { 1843 struct nvkm_bios *bios = init->bios; 1844 u16 port = nv_ro16(bios, init->offset + 1); 1845 u8 index = nv_ro16(bios, init->offset + 3); 1846 u8 mask = nv_ro08(bios, init->offset + 4); 1847 u8 data = nv_ro08(bios, init->offset + 5); 1848 u8 value; 1849 1850 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n", 1851 port, index, mask, data); 1852 init->offset += 6; 1853 1854 value = init_rdvgai(init, port, index) & mask; 1855 init_wrvgai(init, port, index, data | value); 1856 } 1857 1858 /** 1859 * INIT_PLL - opcode 0x79 1860 * 1861 */ 1862 static void 1863 init_pll(struct nvbios_init *init) 1864 { 1865 struct nvkm_bios *bios = init->bios; 1866 u32 reg = nv_ro32(bios, init->offset + 1); 1867 u32 freq = nv_ro16(bios, init->offset + 5) * 10; 1868 1869 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 1870 init->offset += 7; 1871 1872 init_prog_pll(init, reg, freq); 1873 } 1874 1875 /** 1876 * INIT_ZM_REG - opcode 0x7a 1877 * 1878 */ 1879 static void 1880 init_zm_reg(struct nvbios_init *init) 1881 { 1882 struct nvkm_bios *bios = init->bios; 1883 u32 addr = nv_ro32(bios, init->offset + 1); 1884 u32 data = nv_ro32(bios, init->offset + 5); 1885 1886 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data); 1887 init->offset += 9; 1888 1889 if (addr == 0x000200) 1890 data |= 0x00000001; 1891 1892 init_wr32(init, addr, data); 1893 } 1894 1895 /** 1896 * INIT_RAM_RESTRICT_PLL - opcde 0x87 1897 * 1898 */ 1899 static void 1900 init_ram_restrict_pll(struct nvbios_init *init) 1901 { 1902 struct nvkm_bios *bios = init->bios; 1903 u8 type = nv_ro08(bios, init->offset + 1); 1904 u8 count = init_ram_restrict_group_count(init); 1905 u8 strap = init_ram_restrict(init); 1906 u8 cconf; 1907 1908 trace("RAM_RESTRICT_PLL\t0x%02x\n", type); 1909 init->offset += 2; 1910 1911 for (cconf = 0; cconf < count; cconf++) { 1912 u32 freq = nv_ro32(bios, init->offset); 1913 1914 if (cconf == strap) { 1915 trace("%dkHz *\n", freq); 1916 init_prog_pll(init, type, freq); 1917 } else { 1918 trace("%dkHz\n", freq); 1919 } 1920 1921 init->offset += 4; 1922 } 1923 } 1924 1925 /** 1926 * INIT_GPIO - opcode 0x8e 1927 * 1928 */ 1929 static void 1930 init_gpio(struct nvbios_init *init) 1931 { 1932 struct nvkm_gpio *gpio = nvkm_gpio(init->bios); 1933 1934 trace("GPIO\n"); 1935 init->offset += 1; 1936 1937 if (init_exec(init) && gpio && gpio->reset) 1938 gpio->reset(gpio, DCB_GPIO_UNUSED); 1939 } 1940 1941 /** 1942 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f 1943 * 1944 */ 1945 static void 1946 init_ram_restrict_zm_reg_group(struct nvbios_init *init) 1947 { 1948 struct nvkm_bios *bios = init->bios; 1949 u32 addr = nv_ro32(bios, init->offset + 1); 1950 u8 incr = nv_ro08(bios, init->offset + 5); 1951 u8 num = nv_ro08(bios, init->offset + 6); 1952 u8 count = init_ram_restrict_group_count(init); 1953 u8 index = init_ram_restrict(init); 1954 u8 i, j; 1955 1956 trace("RAM_RESTRICT_ZM_REG_GROUP\t" 1957 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num); 1958 init->offset += 7; 1959 1960 for (i = 0; i < num; i++) { 1961 trace("\tR[0x%06x] = {\n", addr); 1962 for (j = 0; j < count; j++) { 1963 u32 data = nv_ro32(bios, init->offset); 1964 1965 if (j == index) { 1966 trace("\t\t0x%08x *\n", data); 1967 init_wr32(init, addr, data); 1968 } else { 1969 trace("\t\t0x%08x\n", data); 1970 } 1971 1972 init->offset += 4; 1973 } 1974 trace("\t}\n"); 1975 addr += incr; 1976 } 1977 } 1978 1979 /** 1980 * INIT_COPY_ZM_REG - opcode 0x90 1981 * 1982 */ 1983 static void 1984 init_copy_zm_reg(struct nvbios_init *init) 1985 { 1986 struct nvkm_bios *bios = init->bios; 1987 u32 sreg = nv_ro32(bios, init->offset + 1); 1988 u32 dreg = nv_ro32(bios, init->offset + 5); 1989 1990 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg); 1991 init->offset += 9; 1992 1993 init_wr32(init, dreg, init_rd32(init, sreg)); 1994 } 1995 1996 /** 1997 * INIT_ZM_REG_GROUP - opcode 0x91 1998 * 1999 */ 2000 static void 2001 init_zm_reg_group(struct nvbios_init *init) 2002 { 2003 struct nvkm_bios *bios = init->bios; 2004 u32 addr = nv_ro32(bios, init->offset + 1); 2005 u8 count = nv_ro08(bios, init->offset + 5); 2006 2007 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr); 2008 init->offset += 6; 2009 2010 while (count--) { 2011 u32 data = nv_ro32(bios, init->offset); 2012 trace("\t0x%08x\n", data); 2013 init_wr32(init, addr, data); 2014 init->offset += 4; 2015 } 2016 } 2017 2018 /** 2019 * INIT_XLAT - opcode 0x96 2020 * 2021 */ 2022 static void 2023 init_xlat(struct nvbios_init *init) 2024 { 2025 struct nvkm_bios *bios = init->bios; 2026 u32 saddr = nv_ro32(bios, init->offset + 1); 2027 u8 sshift = nv_ro08(bios, init->offset + 5); 2028 u8 smask = nv_ro08(bios, init->offset + 6); 2029 u8 index = nv_ro08(bios, init->offset + 7); 2030 u32 daddr = nv_ro32(bios, init->offset + 8); 2031 u32 dmask = nv_ro32(bios, init->offset + 12); 2032 u8 shift = nv_ro08(bios, init->offset + 16); 2033 u32 data; 2034 2035 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= " 2036 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n", 2037 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>", 2038 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift); 2039 init->offset += 17; 2040 2041 data = init_shift(init_rd32(init, saddr), sshift) & smask; 2042 data = init_xlat_(init, index, data) << shift; 2043 init_mask(init, daddr, ~dmask, data); 2044 } 2045 2046 /** 2047 * INIT_ZM_MASK_ADD - opcode 0x97 2048 * 2049 */ 2050 static void 2051 init_zm_mask_add(struct nvbios_init *init) 2052 { 2053 struct nvkm_bios *bios = init->bios; 2054 u32 addr = nv_ro32(bios, init->offset + 1); 2055 u32 mask = nv_ro32(bios, init->offset + 5); 2056 u32 add = nv_ro32(bios, init->offset + 9); 2057 u32 data; 2058 2059 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); 2060 init->offset += 13; 2061 2062 data = init_rd32(init, addr); 2063 data = (data & mask) | ((data + add) & ~mask); 2064 init_wr32(init, addr, data); 2065 } 2066 2067 /** 2068 * INIT_AUXCH - opcode 0x98 2069 * 2070 */ 2071 static void 2072 init_auxch(struct nvbios_init *init) 2073 { 2074 struct nvkm_bios *bios = init->bios; 2075 u32 addr = nv_ro32(bios, init->offset + 1); 2076 u8 count = nv_ro08(bios, init->offset + 5); 2077 2078 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2079 init->offset += 6; 2080 2081 while (count--) { 2082 u8 mask = nv_ro08(bios, init->offset + 0); 2083 u8 data = nv_ro08(bios, init->offset + 1); 2084 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 2085 mask = init_rdauxr(init, addr) & mask; 2086 init_wrauxr(init, addr, mask | data); 2087 init->offset += 2; 2088 } 2089 } 2090 2091 /** 2092 * INIT_AUXCH - opcode 0x99 2093 * 2094 */ 2095 static void 2096 init_zm_auxch(struct nvbios_init *init) 2097 { 2098 struct nvkm_bios *bios = init->bios; 2099 u32 addr = nv_ro32(bios, init->offset + 1); 2100 u8 count = nv_ro08(bios, init->offset + 5); 2101 2102 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2103 init->offset += 6; 2104 2105 while (count--) { 2106 u8 data = nv_ro08(bios, init->offset + 0); 2107 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data); 2108 init_wrauxr(init, addr, data); 2109 init->offset += 1; 2110 } 2111 } 2112 2113 /** 2114 * INIT_I2C_LONG_IF - opcode 0x9a 2115 * 2116 */ 2117 static void 2118 init_i2c_long_if(struct nvbios_init *init) 2119 { 2120 struct nvkm_bios *bios = init->bios; 2121 u8 index = nv_ro08(bios, init->offset + 1); 2122 u8 addr = nv_ro08(bios, init->offset + 2) >> 1; 2123 u8 reglo = nv_ro08(bios, init->offset + 3); 2124 u8 reghi = nv_ro08(bios, init->offset + 4); 2125 u8 mask = nv_ro08(bios, init->offset + 5); 2126 u8 data = nv_ro08(bios, init->offset + 6); 2127 struct nvkm_i2c_port *port; 2128 2129 trace("I2C_LONG_IF\t" 2130 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n", 2131 index, addr, reglo, reghi, mask, data); 2132 init->offset += 7; 2133 2134 port = init_i2c(init, index); 2135 if (port) { 2136 u8 i[2] = { reghi, reglo }; 2137 u8 o[1] = {}; 2138 struct i2c_msg msg[] = { 2139 { .addr = addr, .flags = 0, .len = 2, .buf = i }, 2140 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o } 2141 }; 2142 int ret; 2143 2144 ret = i2c_transfer(&port->adapter, msg, 2); 2145 if (ret == 2 && ((o[0] & mask) == data)) 2146 return; 2147 } 2148 2149 init_exec_set(init, false); 2150 } 2151 2152 /** 2153 * INIT_GPIO_NE - opcode 0xa9 2154 * 2155 */ 2156 static void 2157 init_gpio_ne(struct nvbios_init *init) 2158 { 2159 struct nvkm_bios *bios = init->bios; 2160 struct nvkm_gpio *gpio = nvkm_gpio(bios); 2161 struct dcb_gpio_func func; 2162 u8 count = nv_ro08(bios, init->offset + 1); 2163 u8 idx = 0, ver, len; 2164 u16 data, i; 2165 2166 trace("GPIO_NE\t"); 2167 init->offset += 2; 2168 2169 for (i = init->offset; i < init->offset + count; i++) 2170 cont("0x%02x ", nv_ro08(bios, i)); 2171 cont("\n"); 2172 2173 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) { 2174 if (func.func != DCB_GPIO_UNUSED) { 2175 for (i = init->offset; i < init->offset + count; i++) { 2176 if (func.func == nv_ro08(bios, i)) 2177 break; 2178 } 2179 2180 trace("\tFUNC[0x%02x]", func.func); 2181 if (i == (init->offset + count)) { 2182 cont(" *"); 2183 if (init_exec(init) && gpio && gpio->reset) 2184 gpio->reset(gpio, func.func); 2185 } 2186 cont("\n"); 2187 } 2188 } 2189 2190 init->offset += count; 2191 } 2192 2193 static struct nvbios_init_opcode { 2194 void (*exec)(struct nvbios_init *); 2195 } init_opcode[] = { 2196 [0x32] = { init_io_restrict_prog }, 2197 [0x33] = { init_repeat }, 2198 [0x34] = { init_io_restrict_pll }, 2199 [0x36] = { init_end_repeat }, 2200 [0x37] = { init_copy }, 2201 [0x38] = { init_not }, 2202 [0x39] = { init_io_flag_condition }, 2203 [0x3a] = { init_dp_condition }, 2204 [0x3b] = { init_io_mask_or }, 2205 [0x3c] = { init_io_or }, 2206 [0x47] = { init_andn_reg }, 2207 [0x48] = { init_or_reg }, 2208 [0x49] = { init_idx_addr_latched }, 2209 [0x4a] = { init_io_restrict_pll2 }, 2210 [0x4b] = { init_pll2 }, 2211 [0x4c] = { init_i2c_byte }, 2212 [0x4d] = { init_zm_i2c_byte }, 2213 [0x4e] = { init_zm_i2c }, 2214 [0x4f] = { init_tmds }, 2215 [0x50] = { init_zm_tmds_group }, 2216 [0x51] = { init_cr_idx_adr_latch }, 2217 [0x52] = { init_cr }, 2218 [0x53] = { init_zm_cr }, 2219 [0x54] = { init_zm_cr_group }, 2220 [0x56] = { init_condition_time }, 2221 [0x57] = { init_ltime }, 2222 [0x58] = { init_zm_reg_sequence }, 2223 [0x59] = { init_pll_indirect }, 2224 [0x5a] = { init_zm_reg_indirect }, 2225 [0x5b] = { init_sub_direct }, 2226 [0x5c] = { init_jump }, 2227 [0x5e] = { init_i2c_if }, 2228 [0x5f] = { init_copy_nv_reg }, 2229 [0x62] = { init_zm_index_io }, 2230 [0x63] = { init_compute_mem }, 2231 [0x65] = { init_reset }, 2232 [0x66] = { init_configure_mem }, 2233 [0x67] = { init_configure_clk }, 2234 [0x68] = { init_configure_preinit }, 2235 [0x69] = { init_io }, 2236 [0x6b] = { init_sub }, 2237 [0x6d] = { init_ram_condition }, 2238 [0x6e] = { init_nv_reg }, 2239 [0x6f] = { init_macro }, 2240 [0x71] = { init_done }, 2241 [0x72] = { init_resume }, 2242 [0x73] = { init_strap_condition }, 2243 [0x74] = { init_time }, 2244 [0x75] = { init_condition }, 2245 [0x76] = { init_io_condition }, 2246 [0x77] = { init_zm_reg16 }, 2247 [0x78] = { init_index_io }, 2248 [0x79] = { init_pll }, 2249 [0x7a] = { init_zm_reg }, 2250 [0x87] = { init_ram_restrict_pll }, 2251 [0x8c] = { init_reserved }, 2252 [0x8d] = { init_reserved }, 2253 [0x8e] = { init_gpio }, 2254 [0x8f] = { init_ram_restrict_zm_reg_group }, 2255 [0x90] = { init_copy_zm_reg }, 2256 [0x91] = { init_zm_reg_group }, 2257 [0x92] = { init_reserved }, 2258 [0x96] = { init_xlat }, 2259 [0x97] = { init_zm_mask_add }, 2260 [0x98] = { init_auxch }, 2261 [0x99] = { init_zm_auxch }, 2262 [0x9a] = { init_i2c_long_if }, 2263 [0xa9] = { init_gpio_ne }, 2264 [0xaa] = { init_reserved }, 2265 }; 2266 2267 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0])) 2268 2269 int 2270 nvbios_exec(struct nvbios_init *init) 2271 { 2272 init->nested++; 2273 while (init->offset) { 2274 u8 opcode = nv_ro08(init->bios, init->offset); 2275 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) { 2276 error("unknown opcode 0x%02x\n", opcode); 2277 return -EINVAL; 2278 } 2279 2280 init_opcode[opcode].exec(init); 2281 } 2282 init->nested--; 2283 return 0; 2284 } 2285 2286 int 2287 nvbios_init(struct nvkm_subdev *subdev, bool execute) 2288 { 2289 struct nvkm_bios *bios = nvkm_bios(subdev); 2290 int ret = 0; 2291 int i = -1; 2292 u16 data; 2293 2294 if (execute) 2295 nv_info(bios, "running init tables\n"); 2296 while (!ret && (data = (init_script(bios, ++i)))) { 2297 struct nvbios_init init = { 2298 .subdev = subdev, 2299 .bios = bios, 2300 .offset = data, 2301 .outp = NULL, 2302 .crtc = -1, 2303 .execute = execute ? 1 : 0, 2304 }; 2305 2306 ret = nvbios_exec(&init); 2307 } 2308 2309 /* the vbios parser will run this right after the normal init 2310 * tables, whereas the binary driver appears to run it later. 2311 */ 2312 if (!ret && (data = init_unknown_script(bios))) { 2313 struct nvbios_init init = { 2314 .subdev = subdev, 2315 .bios = bios, 2316 .offset = data, 2317 .outp = NULL, 2318 .crtc = -1, 2319 .execute = execute ? 1 : 0, 2320 }; 2321 2322 ret = nvbios_exec(&init); 2323 } 2324 2325 return ret; 2326 } 2327