1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/bios.h> 25 #include <subdev/bios/bit.h> 26 #include <subdev/bios/bmp.h> 27 #include <subdev/bios/conn.h> 28 #include <subdev/bios/dcb.h> 29 #include <subdev/bios/dp.h> 30 #include <subdev/bios/gpio.h> 31 #include <subdev/bios/init.h> 32 #include <subdev/bios/ramcfg.h> 33 34 #include <subdev/devinit.h> 35 #include <subdev/gpio.h> 36 #include <subdev/i2c.h> 37 #include <subdev/vga.h> 38 39 #define bioslog(lvl, fmt, args...) do { \ 40 nvkm_printk(init->subdev, lvl, info, "0x%04x[%c]: "fmt, \ 41 init->offset, init_exec(init) ? \ 42 '0' + (init->nested - 1) : ' ', ##args); \ 43 } while(0) 44 #define cont(fmt, args...) do { \ 45 if (init->subdev->debug >= NV_DBG_TRACE) \ 46 printk(fmt, ##args); \ 47 } while(0) 48 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args) 49 #define warn(fmt, args...) bioslog(WARN, fmt, ##args) 50 #define error(fmt, args...) bioslog(ERROR, fmt, ##args) 51 52 /****************************************************************************** 53 * init parser control flow helpers 54 *****************************************************************************/ 55 56 static inline bool 57 init_exec(struct nvbios_init *init) 58 { 59 return (init->execute == 1) || ((init->execute & 5) == 5); 60 } 61 62 static inline void 63 init_exec_set(struct nvbios_init *init, bool exec) 64 { 65 if (exec) init->execute &= 0xfd; 66 else init->execute |= 0x02; 67 } 68 69 static inline void 70 init_exec_inv(struct nvbios_init *init) 71 { 72 init->execute ^= 0x02; 73 } 74 75 static inline void 76 init_exec_force(struct nvbios_init *init, bool exec) 77 { 78 if (exec) init->execute |= 0x04; 79 else init->execute &= 0xfb; 80 } 81 82 /****************************************************************************** 83 * init parser wrappers for normal register/i2c/whatever accessors 84 *****************************************************************************/ 85 86 static inline int 87 init_or(struct nvbios_init *init) 88 { 89 if (init_exec(init)) { 90 if (init->outp) 91 return ffs(init->outp->or) - 1; 92 error("script needs OR!!\n"); 93 } 94 return 0; 95 } 96 97 static inline int 98 init_link(struct nvbios_init *init) 99 { 100 if (init_exec(init)) { 101 if (init->outp) 102 return !(init->outp->sorconf.link & 1); 103 error("script needs OR link\n"); 104 } 105 return 0; 106 } 107 108 static inline int 109 init_crtc(struct nvbios_init *init) 110 { 111 if (init_exec(init)) { 112 if (init->crtc >= 0) 113 return init->crtc; 114 error("script needs crtc\n"); 115 } 116 return 0; 117 } 118 119 static u8 120 init_conn(struct nvbios_init *init) 121 { 122 struct nvkm_bios *bios = init->bios; 123 struct nvbios_connE connE; 124 u8 ver, hdr; 125 u32 conn; 126 127 if (init_exec(init)) { 128 if (init->outp) { 129 conn = init->outp->connector; 130 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE); 131 if (conn) 132 return connE.type; 133 } 134 135 error("script needs connector type\n"); 136 } 137 138 return 0xff; 139 } 140 141 static inline u32 142 init_nvreg(struct nvbios_init *init, u32 reg) 143 { 144 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit; 145 146 /* C51 (at least) sometimes has the lower bits set which the VBIOS 147 * interprets to mean that access needs to go through certain IO 148 * ports instead. The NVIDIA binary driver has been seen to access 149 * these through the NV register address, so lets assume we can 150 * do the same 151 */ 152 reg &= ~0x00000003; 153 154 /* GF8+ display scripts need register addresses mangled a bit to 155 * select a specific CRTC/OR 156 */ 157 if (init->bios->subdev.device->card_type >= NV_50) { 158 if (reg & 0x80000000) { 159 reg += init_crtc(init) * 0x800; 160 reg &= ~0x80000000; 161 } 162 163 if (reg & 0x40000000) { 164 reg += init_or(init) * 0x800; 165 reg &= ~0x40000000; 166 if (reg & 0x20000000) { 167 reg += init_link(init) * 0x80; 168 reg &= ~0x20000000; 169 } 170 } 171 } 172 173 if (reg & ~0x00fffffc) 174 warn("unknown bits in register 0x%08x\n", reg); 175 176 return nvkm_devinit_mmio(devinit, reg); 177 } 178 179 static u32 180 init_rd32(struct nvbios_init *init, u32 reg) 181 { 182 struct nvkm_device *device = init->bios->subdev.device; 183 reg = init_nvreg(init, reg); 184 if (reg != ~0 && init_exec(init)) 185 return nvkm_rd32(device, reg); 186 return 0x00000000; 187 } 188 189 static void 190 init_wr32(struct nvbios_init *init, u32 reg, u32 val) 191 { 192 struct nvkm_device *device = init->bios->subdev.device; 193 reg = init_nvreg(init, reg); 194 if (reg != ~0 && init_exec(init)) 195 nvkm_wr32(device, reg, val); 196 } 197 198 static u32 199 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) 200 { 201 struct nvkm_device *device = init->bios->subdev.device; 202 reg = init_nvreg(init, reg); 203 if (reg != ~0 && init_exec(init)) { 204 u32 tmp = nvkm_rd32(device, reg); 205 nvkm_wr32(device, reg, (tmp & ~mask) | val); 206 return tmp; 207 } 208 return 0x00000000; 209 } 210 211 static u8 212 init_rdport(struct nvbios_init *init, u16 port) 213 { 214 if (init_exec(init)) 215 return nvkm_rdport(init->subdev->device, init->crtc, port); 216 return 0x00; 217 } 218 219 static void 220 init_wrport(struct nvbios_init *init, u16 port, u8 value) 221 { 222 if (init_exec(init)) 223 nvkm_wrport(init->subdev->device, init->crtc, port, value); 224 } 225 226 static u8 227 init_rdvgai(struct nvbios_init *init, u16 port, u8 index) 228 { 229 struct nvkm_subdev *subdev = init->subdev; 230 if (init_exec(init)) { 231 int head = init->crtc < 0 ? 0 : init->crtc; 232 return nvkm_rdvgai(subdev->device, head, port, index); 233 } 234 return 0x00; 235 } 236 237 static void 238 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value) 239 { 240 struct nvkm_device *device = init->subdev->device; 241 242 /* force head 0 for updates to cr44, it only exists on first head */ 243 if (device->card_type < NV_50) { 244 if (port == 0x03d4 && index == 0x44) 245 init->crtc = 0; 246 } 247 248 if (init_exec(init)) { 249 int head = init->crtc < 0 ? 0 : init->crtc; 250 nvkm_wrvgai(device, head, port, index, value); 251 } 252 253 /* select head 1 if cr44 write selected it */ 254 if (device->card_type < NV_50) { 255 if (port == 0x03d4 && index == 0x44 && value == 3) 256 init->crtc = 1; 257 } 258 } 259 260 static struct i2c_adapter * 261 init_i2c(struct nvbios_init *init, int index) 262 { 263 struct nvkm_i2c *i2c = init->bios->subdev.device->i2c; 264 struct nvkm_i2c_bus *bus; 265 266 if (index == 0xff) { 267 index = NVKM_I2C_BUS_PRI; 268 if (init->outp && init->outp->i2c_upper_default) 269 index = NVKM_I2C_BUS_SEC; 270 } 271 272 bus = nvkm_i2c_bus_find(i2c, index); 273 return bus ? &bus->i2c : NULL; 274 } 275 276 static int 277 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) 278 { 279 struct i2c_adapter *adap = init_i2c(init, index); 280 if (adap && init_exec(init)) 281 return nvkm_rdi2cr(adap, addr, reg); 282 return -ENODEV; 283 } 284 285 static int 286 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) 287 { 288 struct i2c_adapter *adap = init_i2c(init, index); 289 if (adap && init_exec(init)) 290 return nvkm_wri2cr(adap, addr, reg, val); 291 return -ENODEV; 292 } 293 294 static struct nvkm_i2c_aux * 295 init_aux(struct nvbios_init *init) 296 { 297 struct nvkm_i2c *i2c = init->bios->subdev.device->i2c; 298 if (!init->outp) { 299 if (init_exec(init)) 300 error("script needs output for aux\n"); 301 return NULL; 302 } 303 return nvkm_i2c_aux_find(i2c, init->outp->i2c_index); 304 } 305 306 static u8 307 init_rdauxr(struct nvbios_init *init, u32 addr) 308 { 309 struct nvkm_i2c_aux *aux = init_aux(init); 310 u8 data; 311 312 if (aux && init_exec(init)) { 313 int ret = nvkm_rdaux(aux, addr, &data, 1); 314 if (ret == 0) 315 return data; 316 trace("auxch read failed with %d\n", ret); 317 } 318 319 return 0x00; 320 } 321 322 static int 323 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) 324 { 325 struct nvkm_i2c_aux *aux = init_aux(init); 326 if (aux && init_exec(init)) { 327 int ret = nvkm_wraux(aux, addr, &data, 1); 328 if (ret) 329 trace("auxch write failed with %d\n", ret); 330 return ret; 331 } 332 return -ENODEV; 333 } 334 335 static void 336 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) 337 { 338 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit; 339 if (init_exec(init)) { 340 int ret = nvkm_devinit_pll_set(devinit, id, freq); 341 if (ret) 342 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq); 343 } 344 } 345 346 /****************************************************************************** 347 * parsing of bios structures that are required to execute init tables 348 *****************************************************************************/ 349 350 static u16 351 init_table(struct nvkm_bios *bios, u16 *len) 352 { 353 struct bit_entry bit_I; 354 355 if (!bit_entry(bios, 'I', &bit_I)) { 356 *len = bit_I.length; 357 return bit_I.offset; 358 } 359 360 if (bmp_version(bios) >= 0x0510) { 361 *len = 14; 362 return bios->bmp_offset + 75; 363 } 364 365 return 0x0000; 366 } 367 368 static u16 369 init_table_(struct nvbios_init *init, u16 offset, const char *name) 370 { 371 struct nvkm_bios *bios = init->bios; 372 u16 len, data = init_table(bios, &len); 373 if (data) { 374 if (len >= offset + 2) { 375 data = nvbios_rd16(bios, data + offset); 376 if (data) 377 return data; 378 379 warn("%s pointer invalid\n", name); 380 return 0x0000; 381 } 382 383 warn("init data too short for %s pointer", name); 384 return 0x0000; 385 } 386 387 warn("init data not found\n"); 388 return 0x0000; 389 } 390 391 #define init_script_table(b) init_table_((b), 0x00, "script table") 392 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table") 393 #define init_macro_table(b) init_table_((b), 0x04, "macro table") 394 #define init_condition_table(b) init_table_((b), 0x06, "condition table") 395 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table") 396 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table") 397 #define init_function_table(b) init_table_((b), 0x0c, "function table") 398 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); 399 400 static u16 401 init_script(struct nvkm_bios *bios, int index) 402 { 403 struct nvbios_init init = { .bios = bios }; 404 u16 bmp_ver = bmp_version(bios), data; 405 406 if (bmp_ver && bmp_ver < 0x0510) { 407 if (index > 1 || bmp_ver < 0x0100) 408 return 0x0000; 409 410 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18); 411 return nvbios_rd16(bios, data + (index * 2)); 412 } 413 414 data = init_script_table(&init); 415 if (data) 416 return nvbios_rd16(bios, data + (index * 2)); 417 418 return 0x0000; 419 } 420 421 static u16 422 init_unknown_script(struct nvkm_bios *bios) 423 { 424 u16 len, data = init_table(bios, &len); 425 if (data && len >= 16) 426 return nvbios_rd16(bios, data + 14); 427 return 0x0000; 428 } 429 430 static u8 431 init_ram_restrict_group_count(struct nvbios_init *init) 432 { 433 return nvbios_ramcfg_count(init->bios); 434 } 435 436 static u8 437 init_ram_restrict(struct nvbios_init *init) 438 { 439 /* This appears to be the behaviour of the VBIOS parser, and *is* 440 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to 441 * avoid fucking up the memory controller (somehow) by reading it 442 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode. 443 * 444 * Preserving the non-caching behaviour on earlier chipsets just 445 * in case *not* re-reading the strap causes similar breakage. 446 */ 447 if (!init->ramcfg || init->bios->version.major < 0x70) 448 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev); 449 return (init->ramcfg & 0x7fffffff); 450 } 451 452 static u8 453 init_xlat_(struct nvbios_init *init, u8 index, u8 offset) 454 { 455 struct nvkm_bios *bios = init->bios; 456 u16 table = init_xlat_table(init); 457 if (table) { 458 u16 data = nvbios_rd16(bios, table + (index * 2)); 459 if (data) 460 return nvbios_rd08(bios, data + offset); 461 warn("xlat table pointer %d invalid\n", index); 462 } 463 return 0x00; 464 } 465 466 /****************************************************************************** 467 * utility functions used by various init opcode handlers 468 *****************************************************************************/ 469 470 static bool 471 init_condition_met(struct nvbios_init *init, u8 cond) 472 { 473 struct nvkm_bios *bios = init->bios; 474 u16 table = init_condition_table(init); 475 if (table) { 476 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0); 477 u32 msk = nvbios_rd32(bios, table + (cond * 12) + 4); 478 u32 val = nvbios_rd32(bios, table + (cond * 12) + 8); 479 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n", 480 cond, reg, msk, val); 481 return (init_rd32(init, reg) & msk) == val; 482 } 483 return false; 484 } 485 486 static bool 487 init_io_condition_met(struct nvbios_init *init, u8 cond) 488 { 489 struct nvkm_bios *bios = init->bios; 490 u16 table = init_io_condition_table(init); 491 if (table) { 492 u16 port = nvbios_rd16(bios, table + (cond * 5) + 0); 493 u8 index = nvbios_rd08(bios, table + (cond * 5) + 2); 494 u8 mask = nvbios_rd08(bios, table + (cond * 5) + 3); 495 u8 value = nvbios_rd08(bios, table + (cond * 5) + 4); 496 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n", 497 cond, port, index, mask, value); 498 return (init_rdvgai(init, port, index) & mask) == value; 499 } 500 return false; 501 } 502 503 static bool 504 init_io_flag_condition_met(struct nvbios_init *init, u8 cond) 505 { 506 struct nvkm_bios *bios = init->bios; 507 u16 table = init_io_flag_condition_table(init); 508 if (table) { 509 u16 port = nvbios_rd16(bios, table + (cond * 9) + 0); 510 u8 index = nvbios_rd08(bios, table + (cond * 9) + 2); 511 u8 mask = nvbios_rd08(bios, table + (cond * 9) + 3); 512 u8 shift = nvbios_rd08(bios, table + (cond * 9) + 4); 513 u16 data = nvbios_rd16(bios, table + (cond * 9) + 5); 514 u8 dmask = nvbios_rd08(bios, table + (cond * 9) + 7); 515 u8 value = nvbios_rd08(bios, table + (cond * 9) + 8); 516 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift; 517 return (nvbios_rd08(bios, data + ioval) & dmask) == value; 518 } 519 return false; 520 } 521 522 static inline u32 523 init_shift(u32 data, u8 shift) 524 { 525 if (shift < 0x80) 526 return data >> shift; 527 return data << (0x100 - shift); 528 } 529 530 static u32 531 init_tmds_reg(struct nvbios_init *init, u8 tmds) 532 { 533 /* For mlv < 0x80, it is an index into a table of TMDS base addresses. 534 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 535 * CR58 for CR57 = 0 to index a table of offsets to the basic 536 * 0x6808b0 address. 537 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 538 * CR58 for CR57 = 0 to index a table of offsets to the basic 539 * 0x6808b0 address, and then flip the offset by 8. 540 */ 541 const int pramdac_offset[13] = { 542 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 543 const u32 pramdac_table[4] = { 544 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 545 546 if (tmds >= 0x80) { 547 if (init->outp) { 548 u32 dacoffset = pramdac_offset[init->outp->or]; 549 if (tmds == 0x81) 550 dacoffset ^= 8; 551 return 0x6808b0 + dacoffset; 552 } 553 554 if (init_exec(init)) 555 error("tmds opcodes need dcb\n"); 556 } else { 557 if (tmds < ARRAY_SIZE(pramdac_table)) 558 return pramdac_table[tmds]; 559 560 error("tmds selector 0x%02x unknown\n", tmds); 561 } 562 563 return 0; 564 } 565 566 /****************************************************************************** 567 * init opcode handlers 568 *****************************************************************************/ 569 570 /** 571 * init_reserved - stub for various unknown/unused single-byte opcodes 572 * 573 */ 574 static void 575 init_reserved(struct nvbios_init *init) 576 { 577 u8 opcode = nvbios_rd08(init->bios, init->offset); 578 u8 length, i; 579 580 switch (opcode) { 581 case 0xaa: 582 length = 4; 583 break; 584 default: 585 length = 1; 586 break; 587 } 588 589 trace("RESERVED 0x%02x\t", opcode); 590 for (i = 1; i < length; i++) 591 cont(" 0x%02x", nvbios_rd08(init->bios, init->offset + i)); 592 cont("\n"); 593 init->offset += length; 594 } 595 596 /** 597 * INIT_DONE - opcode 0x71 598 * 599 */ 600 static void 601 init_done(struct nvbios_init *init) 602 { 603 trace("DONE\n"); 604 init->offset = 0x0000; 605 } 606 607 /** 608 * INIT_IO_RESTRICT_PROG - opcode 0x32 609 * 610 */ 611 static void 612 init_io_restrict_prog(struct nvbios_init *init) 613 { 614 struct nvkm_bios *bios = init->bios; 615 u16 port = nvbios_rd16(bios, init->offset + 1); 616 u8 index = nvbios_rd08(bios, init->offset + 3); 617 u8 mask = nvbios_rd08(bios, init->offset + 4); 618 u8 shift = nvbios_rd08(bios, init->offset + 5); 619 u8 count = nvbios_rd08(bios, init->offset + 6); 620 u32 reg = nvbios_rd32(bios, init->offset + 7); 621 u8 conf, i; 622 623 trace("IO_RESTRICT_PROG\tR[0x%06x] = " 624 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n", 625 reg, port, index, mask, shift); 626 init->offset += 11; 627 628 conf = (init_rdvgai(init, port, index) & mask) >> shift; 629 for (i = 0; i < count; i++) { 630 u32 data = nvbios_rd32(bios, init->offset); 631 632 if (i == conf) { 633 trace("\t0x%08x *\n", data); 634 init_wr32(init, reg, data); 635 } else { 636 trace("\t0x%08x\n", data); 637 } 638 639 init->offset += 4; 640 } 641 trace("}]\n"); 642 } 643 644 /** 645 * INIT_REPEAT - opcode 0x33 646 * 647 */ 648 static void 649 init_repeat(struct nvbios_init *init) 650 { 651 struct nvkm_bios *bios = init->bios; 652 u8 count = nvbios_rd08(bios, init->offset + 1); 653 u16 repeat = init->repeat; 654 655 trace("REPEAT\t0x%02x\n", count); 656 init->offset += 2; 657 658 init->repeat = init->offset; 659 init->repend = init->offset; 660 while (count--) { 661 init->offset = init->repeat; 662 nvbios_exec(init); 663 if (count) 664 trace("REPEAT\t0x%02x\n", count); 665 } 666 init->offset = init->repend; 667 init->repeat = repeat; 668 } 669 670 /** 671 * INIT_IO_RESTRICT_PLL - opcode 0x34 672 * 673 */ 674 static void 675 init_io_restrict_pll(struct nvbios_init *init) 676 { 677 struct nvkm_bios *bios = init->bios; 678 u16 port = nvbios_rd16(bios, init->offset + 1); 679 u8 index = nvbios_rd08(bios, init->offset + 3); 680 u8 mask = nvbios_rd08(bios, init->offset + 4); 681 u8 shift = nvbios_rd08(bios, init->offset + 5); 682 s8 iofc = nvbios_rd08(bios, init->offset + 6); 683 u8 count = nvbios_rd08(bios, init->offset + 7); 684 u32 reg = nvbios_rd32(bios, init->offset + 8); 685 u8 conf, i; 686 687 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= " 688 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n", 689 reg, port, index, mask, shift, iofc); 690 init->offset += 12; 691 692 conf = (init_rdvgai(init, port, index) & mask) >> shift; 693 for (i = 0; i < count; i++) { 694 u32 freq = nvbios_rd16(bios, init->offset) * 10; 695 696 if (i == conf) { 697 trace("\t%dkHz *\n", freq); 698 if (iofc > 0 && init_io_flag_condition_met(init, iofc)) 699 freq *= 2; 700 init_prog_pll(init, reg, freq); 701 } else { 702 trace("\t%dkHz\n", freq); 703 } 704 705 init->offset += 2; 706 } 707 trace("}]\n"); 708 } 709 710 /** 711 * INIT_END_REPEAT - opcode 0x36 712 * 713 */ 714 static void 715 init_end_repeat(struct nvbios_init *init) 716 { 717 trace("END_REPEAT\n"); 718 init->offset += 1; 719 720 if (init->repeat) { 721 init->repend = init->offset; 722 init->offset = 0; 723 } 724 } 725 726 /** 727 * INIT_COPY - opcode 0x37 728 * 729 */ 730 static void 731 init_copy(struct nvbios_init *init) 732 { 733 struct nvkm_bios *bios = init->bios; 734 u32 reg = nvbios_rd32(bios, init->offset + 1); 735 u8 shift = nvbios_rd08(bios, init->offset + 5); 736 u8 smask = nvbios_rd08(bios, init->offset + 6); 737 u16 port = nvbios_rd16(bios, init->offset + 7); 738 u8 index = nvbios_rd08(bios, init->offset + 9); 739 u8 mask = nvbios_rd08(bios, init->offset + 10); 740 u8 data; 741 742 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= " 743 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n", 744 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", 745 (shift & 0x80) ? (0x100 - shift) : shift, smask); 746 init->offset += 11; 747 748 data = init_rdvgai(init, port, index) & mask; 749 data |= init_shift(init_rd32(init, reg), shift) & smask; 750 init_wrvgai(init, port, index, data); 751 } 752 753 /** 754 * INIT_NOT - opcode 0x38 755 * 756 */ 757 static void 758 init_not(struct nvbios_init *init) 759 { 760 trace("NOT\n"); 761 init->offset += 1; 762 init_exec_inv(init); 763 } 764 765 /** 766 * INIT_IO_FLAG_CONDITION - opcode 0x39 767 * 768 */ 769 static void 770 init_io_flag_condition(struct nvbios_init *init) 771 { 772 struct nvkm_bios *bios = init->bios; 773 u8 cond = nvbios_rd08(bios, init->offset + 1); 774 775 trace("IO_FLAG_CONDITION\t0x%02x\n", cond); 776 init->offset += 2; 777 778 if (!init_io_flag_condition_met(init, cond)) 779 init_exec_set(init, false); 780 } 781 782 /** 783 * INIT_DP_CONDITION - opcode 0x3a 784 * 785 */ 786 static void 787 init_dp_condition(struct nvbios_init *init) 788 { 789 struct nvkm_bios *bios = init->bios; 790 struct nvbios_dpout info; 791 u8 cond = nvbios_rd08(bios, init->offset + 1); 792 u8 unkn = nvbios_rd08(bios, init->offset + 2); 793 u8 ver, hdr, cnt, len; 794 u16 data; 795 796 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn); 797 init->offset += 3; 798 799 switch (cond) { 800 case 0: 801 if (init_conn(init) != DCB_CONNECTOR_eDP) 802 init_exec_set(init, false); 803 break; 804 case 1: 805 case 2: 806 if ( init->outp && 807 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP, 808 (init->outp->or << 0) | 809 (init->outp->sorconf.link << 6), 810 &ver, &hdr, &cnt, &len, &info))) 811 { 812 if (!(info.flags & cond)) 813 init_exec_set(init, false); 814 break; 815 } 816 817 if (init_exec(init)) 818 warn("script needs dp output table data\n"); 819 break; 820 case 5: 821 if (!(init_rdauxr(init, 0x0d) & 1)) 822 init_exec_set(init, false); 823 break; 824 default: 825 warn("unknown dp condition 0x%02x\n", cond); 826 break; 827 } 828 } 829 830 /** 831 * INIT_IO_MASK_OR - opcode 0x3b 832 * 833 */ 834 static void 835 init_io_mask_or(struct nvbios_init *init) 836 { 837 struct nvkm_bios *bios = init->bios; 838 u8 index = nvbios_rd08(bios, init->offset + 1); 839 u8 or = init_or(init); 840 u8 data; 841 842 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or); 843 init->offset += 2; 844 845 data = init_rdvgai(init, 0x03d4, index); 846 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); 847 } 848 849 /** 850 * INIT_IO_OR - opcode 0x3c 851 * 852 */ 853 static void 854 init_io_or(struct nvbios_init *init) 855 { 856 struct nvkm_bios *bios = init->bios; 857 u8 index = nvbios_rd08(bios, init->offset + 1); 858 u8 or = init_or(init); 859 u8 data; 860 861 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or); 862 init->offset += 2; 863 864 data = init_rdvgai(init, 0x03d4, index); 865 init_wrvgai(init, 0x03d4, index, data | (1 << or)); 866 } 867 868 /** 869 * INIT_ANDN_REG - opcode 0x47 870 * 871 */ 872 static void 873 init_andn_reg(struct nvbios_init *init) 874 { 875 struct nvkm_bios *bios = init->bios; 876 u32 reg = nvbios_rd32(bios, init->offset + 1); 877 u32 mask = nvbios_rd32(bios, init->offset + 5); 878 879 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask); 880 init->offset += 9; 881 882 init_mask(init, reg, mask, 0); 883 } 884 885 /** 886 * INIT_OR_REG - opcode 0x48 887 * 888 */ 889 static void 890 init_or_reg(struct nvbios_init *init) 891 { 892 struct nvkm_bios *bios = init->bios; 893 u32 reg = nvbios_rd32(bios, init->offset + 1); 894 u32 mask = nvbios_rd32(bios, init->offset + 5); 895 896 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask); 897 init->offset += 9; 898 899 init_mask(init, reg, 0, mask); 900 } 901 902 /** 903 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49 904 * 905 */ 906 static void 907 init_idx_addr_latched(struct nvbios_init *init) 908 { 909 struct nvkm_bios *bios = init->bios; 910 u32 creg = nvbios_rd32(bios, init->offset + 1); 911 u32 dreg = nvbios_rd32(bios, init->offset + 5); 912 u32 mask = nvbios_rd32(bios, init->offset + 9); 913 u32 data = nvbios_rd32(bios, init->offset + 13); 914 u8 count = nvbios_rd08(bios, init->offset + 17); 915 916 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg); 917 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data); 918 init->offset += 18; 919 920 while (count--) { 921 u8 iaddr = nvbios_rd08(bios, init->offset + 0); 922 u8 idata = nvbios_rd08(bios, init->offset + 1); 923 924 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata); 925 init->offset += 2; 926 927 init_wr32(init, dreg, idata); 928 init_mask(init, creg, ~mask, data | iaddr); 929 } 930 } 931 932 /** 933 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a 934 * 935 */ 936 static void 937 init_io_restrict_pll2(struct nvbios_init *init) 938 { 939 struct nvkm_bios *bios = init->bios; 940 u16 port = nvbios_rd16(bios, init->offset + 1); 941 u8 index = nvbios_rd08(bios, init->offset + 3); 942 u8 mask = nvbios_rd08(bios, init->offset + 4); 943 u8 shift = nvbios_rd08(bios, init->offset + 5); 944 u8 count = nvbios_rd08(bios, init->offset + 6); 945 u32 reg = nvbios_rd32(bios, init->offset + 7); 946 u8 conf, i; 947 948 trace("IO_RESTRICT_PLL2\t" 949 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n", 950 reg, port, index, mask, shift); 951 init->offset += 11; 952 953 conf = (init_rdvgai(init, port, index) & mask) >> shift; 954 for (i = 0; i < count; i++) { 955 u32 freq = nvbios_rd32(bios, init->offset); 956 if (i == conf) { 957 trace("\t%dkHz *\n", freq); 958 init_prog_pll(init, reg, freq); 959 } else { 960 trace("\t%dkHz\n", freq); 961 } 962 init->offset += 4; 963 } 964 trace("}]\n"); 965 } 966 967 /** 968 * INIT_PLL2 - opcode 0x4b 969 * 970 */ 971 static void 972 init_pll2(struct nvbios_init *init) 973 { 974 struct nvkm_bios *bios = init->bios; 975 u32 reg = nvbios_rd32(bios, init->offset + 1); 976 u32 freq = nvbios_rd32(bios, init->offset + 5); 977 978 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 979 init->offset += 9; 980 981 init_prog_pll(init, reg, freq); 982 } 983 984 /** 985 * INIT_I2C_BYTE - opcode 0x4c 986 * 987 */ 988 static void 989 init_i2c_byte(struct nvbios_init *init) 990 { 991 struct nvkm_bios *bios = init->bios; 992 u8 index = nvbios_rd08(bios, init->offset + 1); 993 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 994 u8 count = nvbios_rd08(bios, init->offset + 3); 995 996 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 997 init->offset += 4; 998 999 while (count--) { 1000 u8 reg = nvbios_rd08(bios, init->offset + 0); 1001 u8 mask = nvbios_rd08(bios, init->offset + 1); 1002 u8 data = nvbios_rd08(bios, init->offset + 2); 1003 int val; 1004 1005 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); 1006 init->offset += 3; 1007 1008 val = init_rdi2cr(init, index, addr, reg); 1009 if (val < 0) 1010 continue; 1011 init_wri2cr(init, index, addr, reg, (val & mask) | data); 1012 } 1013 } 1014 1015 /** 1016 * INIT_ZM_I2C_BYTE - opcode 0x4d 1017 * 1018 */ 1019 static void 1020 init_zm_i2c_byte(struct nvbios_init *init) 1021 { 1022 struct nvkm_bios *bios = init->bios; 1023 u8 index = nvbios_rd08(bios, init->offset + 1); 1024 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 1025 u8 count = nvbios_rd08(bios, init->offset + 3); 1026 1027 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 1028 init->offset += 4; 1029 1030 while (count--) { 1031 u8 reg = nvbios_rd08(bios, init->offset + 0); 1032 u8 data = nvbios_rd08(bios, init->offset + 1); 1033 1034 trace("\t[0x%02x] = 0x%02x\n", reg, data); 1035 init->offset += 2; 1036 1037 init_wri2cr(init, index, addr, reg, data); 1038 } 1039 } 1040 1041 /** 1042 * INIT_ZM_I2C - opcode 0x4e 1043 * 1044 */ 1045 static void 1046 init_zm_i2c(struct nvbios_init *init) 1047 { 1048 struct nvkm_bios *bios = init->bios; 1049 u8 index = nvbios_rd08(bios, init->offset + 1); 1050 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 1051 u8 count = nvbios_rd08(bios, init->offset + 3); 1052 u8 data[256], i; 1053 1054 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr); 1055 init->offset += 4; 1056 1057 for (i = 0; i < count; i++) { 1058 data[i] = nvbios_rd08(bios, init->offset); 1059 trace("\t0x%02x\n", data[i]); 1060 init->offset++; 1061 } 1062 1063 if (init_exec(init)) { 1064 struct i2c_adapter *adap = init_i2c(init, index); 1065 struct i2c_msg msg = { 1066 .addr = addr, .flags = 0, .len = count, .buf = data, 1067 }; 1068 int ret; 1069 1070 if (adap && (ret = i2c_transfer(adap, &msg, 1)) != 1) 1071 warn("i2c wr failed, %d\n", ret); 1072 } 1073 } 1074 1075 /** 1076 * INIT_TMDS - opcode 0x4f 1077 * 1078 */ 1079 static void 1080 init_tmds(struct nvbios_init *init) 1081 { 1082 struct nvkm_bios *bios = init->bios; 1083 u8 tmds = nvbios_rd08(bios, init->offset + 1); 1084 u8 addr = nvbios_rd08(bios, init->offset + 2); 1085 u8 mask = nvbios_rd08(bios, init->offset + 3); 1086 u8 data = nvbios_rd08(bios, init->offset + 4); 1087 u32 reg = init_tmds_reg(init, tmds); 1088 1089 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n", 1090 tmds, addr, mask, data); 1091 init->offset += 5; 1092 1093 if (reg == 0) 1094 return; 1095 1096 init_wr32(init, reg + 0, addr | 0x00010000); 1097 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); 1098 init_wr32(init, reg + 0, addr); 1099 } 1100 1101 /** 1102 * INIT_ZM_TMDS_GROUP - opcode 0x50 1103 * 1104 */ 1105 static void 1106 init_zm_tmds_group(struct nvbios_init *init) 1107 { 1108 struct nvkm_bios *bios = init->bios; 1109 u8 tmds = nvbios_rd08(bios, init->offset + 1); 1110 u8 count = nvbios_rd08(bios, init->offset + 2); 1111 u32 reg = init_tmds_reg(init, tmds); 1112 1113 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds); 1114 init->offset += 3; 1115 1116 while (count--) { 1117 u8 addr = nvbios_rd08(bios, init->offset + 0); 1118 u8 data = nvbios_rd08(bios, init->offset + 1); 1119 1120 trace("\t[0x%02x] = 0x%02x\n", addr, data); 1121 init->offset += 2; 1122 1123 init_wr32(init, reg + 4, data); 1124 init_wr32(init, reg + 0, addr); 1125 } 1126 } 1127 1128 /** 1129 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51 1130 * 1131 */ 1132 static void 1133 init_cr_idx_adr_latch(struct nvbios_init *init) 1134 { 1135 struct nvkm_bios *bios = init->bios; 1136 u8 addr0 = nvbios_rd08(bios, init->offset + 1); 1137 u8 addr1 = nvbios_rd08(bios, init->offset + 2); 1138 u8 base = nvbios_rd08(bios, init->offset + 3); 1139 u8 count = nvbios_rd08(bios, init->offset + 4); 1140 u8 save0; 1141 1142 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1); 1143 init->offset += 5; 1144 1145 save0 = init_rdvgai(init, 0x03d4, addr0); 1146 while (count--) { 1147 u8 data = nvbios_rd08(bios, init->offset); 1148 1149 trace("\t\t[0x%02x] = 0x%02x\n", base, data); 1150 init->offset += 1; 1151 1152 init_wrvgai(init, 0x03d4, addr0, base++); 1153 init_wrvgai(init, 0x03d4, addr1, data); 1154 } 1155 init_wrvgai(init, 0x03d4, addr0, save0); 1156 } 1157 1158 /** 1159 * INIT_CR - opcode 0x52 1160 * 1161 */ 1162 static void 1163 init_cr(struct nvbios_init *init) 1164 { 1165 struct nvkm_bios *bios = init->bios; 1166 u8 addr = nvbios_rd08(bios, init->offset + 1); 1167 u8 mask = nvbios_rd08(bios, init->offset + 2); 1168 u8 data = nvbios_rd08(bios, init->offset + 3); 1169 u8 val; 1170 1171 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 1172 init->offset += 4; 1173 1174 val = init_rdvgai(init, 0x03d4, addr) & mask; 1175 init_wrvgai(init, 0x03d4, addr, val | data); 1176 } 1177 1178 /** 1179 * INIT_ZM_CR - opcode 0x53 1180 * 1181 */ 1182 static void 1183 init_zm_cr(struct nvbios_init *init) 1184 { 1185 struct nvkm_bios *bios = init->bios; 1186 u8 addr = nvbios_rd08(bios, init->offset + 1); 1187 u8 data = nvbios_rd08(bios, init->offset + 2); 1188 1189 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data); 1190 init->offset += 3; 1191 1192 init_wrvgai(init, 0x03d4, addr, data); 1193 } 1194 1195 /** 1196 * INIT_ZM_CR_GROUP - opcode 0x54 1197 * 1198 */ 1199 static void 1200 init_zm_cr_group(struct nvbios_init *init) 1201 { 1202 struct nvkm_bios *bios = init->bios; 1203 u8 count = nvbios_rd08(bios, init->offset + 1); 1204 1205 trace("ZM_CR_GROUP\n"); 1206 init->offset += 2; 1207 1208 while (count--) { 1209 u8 addr = nvbios_rd08(bios, init->offset + 0); 1210 u8 data = nvbios_rd08(bios, init->offset + 1); 1211 1212 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data); 1213 init->offset += 2; 1214 1215 init_wrvgai(init, 0x03d4, addr, data); 1216 } 1217 } 1218 1219 /** 1220 * INIT_CONDITION_TIME - opcode 0x56 1221 * 1222 */ 1223 static void 1224 init_condition_time(struct nvbios_init *init) 1225 { 1226 struct nvkm_bios *bios = init->bios; 1227 u8 cond = nvbios_rd08(bios, init->offset + 1); 1228 u8 retry = nvbios_rd08(bios, init->offset + 2); 1229 u8 wait = min((u16)retry * 50, 100); 1230 1231 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry); 1232 init->offset += 3; 1233 1234 if (!init_exec(init)) 1235 return; 1236 1237 while (wait--) { 1238 if (init_condition_met(init, cond)) 1239 return; 1240 mdelay(20); 1241 } 1242 1243 init_exec_set(init, false); 1244 } 1245 1246 /** 1247 * INIT_LTIME - opcode 0x57 1248 * 1249 */ 1250 static void 1251 init_ltime(struct nvbios_init *init) 1252 { 1253 struct nvkm_bios *bios = init->bios; 1254 u16 msec = nvbios_rd16(bios, init->offset + 1); 1255 1256 trace("LTIME\t0x%04x\n", msec); 1257 init->offset += 3; 1258 1259 if (init_exec(init)) 1260 mdelay(msec); 1261 } 1262 1263 /** 1264 * INIT_ZM_REG_SEQUENCE - opcode 0x58 1265 * 1266 */ 1267 static void 1268 init_zm_reg_sequence(struct nvbios_init *init) 1269 { 1270 struct nvkm_bios *bios = init->bios; 1271 u32 base = nvbios_rd32(bios, init->offset + 1); 1272 u8 count = nvbios_rd08(bios, init->offset + 5); 1273 1274 trace("ZM_REG_SEQUENCE\t0x%02x\n", count); 1275 init->offset += 6; 1276 1277 while (count--) { 1278 u32 data = nvbios_rd32(bios, init->offset); 1279 1280 trace("\t\tR[0x%06x] = 0x%08x\n", base, data); 1281 init->offset += 4; 1282 1283 init_wr32(init, base, data); 1284 base += 4; 1285 } 1286 } 1287 1288 /** 1289 * INIT_PLL_INDIRECT - opcode 0x59 1290 * 1291 */ 1292 static void 1293 init_pll_indirect(struct nvbios_init *init) 1294 { 1295 struct nvkm_bios *bios = init->bios; 1296 u32 reg = nvbios_rd32(bios, init->offset + 1); 1297 u16 addr = nvbios_rd16(bios, init->offset + 5); 1298 u32 freq = (u32)nvbios_rd16(bios, addr) * 1000; 1299 1300 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n", 1301 reg, addr, freq); 1302 init->offset += 7; 1303 1304 init_prog_pll(init, reg, freq); 1305 } 1306 1307 /** 1308 * INIT_ZM_REG_INDIRECT - opcode 0x5a 1309 * 1310 */ 1311 static void 1312 init_zm_reg_indirect(struct nvbios_init *init) 1313 { 1314 struct nvkm_bios *bios = init->bios; 1315 u32 reg = nvbios_rd32(bios, init->offset + 1); 1316 u16 addr = nvbios_rd16(bios, init->offset + 5); 1317 u32 data = nvbios_rd32(bios, addr); 1318 1319 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n", 1320 reg, addr, data); 1321 init->offset += 7; 1322 1323 init_wr32(init, addr, data); 1324 } 1325 1326 /** 1327 * INIT_SUB_DIRECT - opcode 0x5b 1328 * 1329 */ 1330 static void 1331 init_sub_direct(struct nvbios_init *init) 1332 { 1333 struct nvkm_bios *bios = init->bios; 1334 u16 addr = nvbios_rd16(bios, init->offset + 1); 1335 u16 save; 1336 1337 trace("SUB_DIRECT\t0x%04x\n", addr); 1338 1339 if (init_exec(init)) { 1340 save = init->offset; 1341 init->offset = addr; 1342 if (nvbios_exec(init)) { 1343 error("error parsing sub-table\n"); 1344 return; 1345 } 1346 init->offset = save; 1347 } 1348 1349 init->offset += 3; 1350 } 1351 1352 /** 1353 * INIT_JUMP - opcode 0x5c 1354 * 1355 */ 1356 static void 1357 init_jump(struct nvbios_init *init) 1358 { 1359 struct nvkm_bios *bios = init->bios; 1360 u16 offset = nvbios_rd16(bios, init->offset + 1); 1361 1362 trace("JUMP\t0x%04x\n", offset); 1363 1364 if (init_exec(init)) 1365 init->offset = offset; 1366 else 1367 init->offset += 3; 1368 } 1369 1370 /** 1371 * INIT_I2C_IF - opcode 0x5e 1372 * 1373 */ 1374 static void 1375 init_i2c_if(struct nvbios_init *init) 1376 { 1377 struct nvkm_bios *bios = init->bios; 1378 u8 index = nvbios_rd08(bios, init->offset + 1); 1379 u8 addr = nvbios_rd08(bios, init->offset + 2); 1380 u8 reg = nvbios_rd08(bios, init->offset + 3); 1381 u8 mask = nvbios_rd08(bios, init->offset + 4); 1382 u8 data = nvbios_rd08(bios, init->offset + 5); 1383 u8 value; 1384 1385 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n", 1386 index, addr, reg, mask, data); 1387 init->offset += 6; 1388 init_exec_force(init, true); 1389 1390 value = init_rdi2cr(init, index, addr, reg); 1391 if ((value & mask) != data) 1392 init_exec_set(init, false); 1393 1394 init_exec_force(init, false); 1395 } 1396 1397 /** 1398 * INIT_COPY_NV_REG - opcode 0x5f 1399 * 1400 */ 1401 static void 1402 init_copy_nv_reg(struct nvbios_init *init) 1403 { 1404 struct nvkm_bios *bios = init->bios; 1405 u32 sreg = nvbios_rd32(bios, init->offset + 1); 1406 u8 shift = nvbios_rd08(bios, init->offset + 5); 1407 u32 smask = nvbios_rd32(bios, init->offset + 6); 1408 u32 sxor = nvbios_rd32(bios, init->offset + 10); 1409 u32 dreg = nvbios_rd32(bios, init->offset + 14); 1410 u32 dmask = nvbios_rd32(bios, init->offset + 18); 1411 u32 data; 1412 1413 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= " 1414 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n", 1415 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>", 1416 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor); 1417 init->offset += 22; 1418 1419 data = init_shift(init_rd32(init, sreg), shift); 1420 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor); 1421 } 1422 1423 /** 1424 * INIT_ZM_INDEX_IO - opcode 0x62 1425 * 1426 */ 1427 static void 1428 init_zm_index_io(struct nvbios_init *init) 1429 { 1430 struct nvkm_bios *bios = init->bios; 1431 u16 port = nvbios_rd16(bios, init->offset + 1); 1432 u8 index = nvbios_rd08(bios, init->offset + 3); 1433 u8 data = nvbios_rd08(bios, init->offset + 4); 1434 1435 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data); 1436 init->offset += 5; 1437 1438 init_wrvgai(init, port, index, data); 1439 } 1440 1441 /** 1442 * INIT_COMPUTE_MEM - opcode 0x63 1443 * 1444 */ 1445 static void 1446 init_compute_mem(struct nvbios_init *init) 1447 { 1448 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit; 1449 1450 trace("COMPUTE_MEM\n"); 1451 init->offset += 1; 1452 1453 init_exec_force(init, true); 1454 if (init_exec(init)) 1455 nvkm_devinit_meminit(devinit); 1456 init_exec_force(init, false); 1457 } 1458 1459 /** 1460 * INIT_RESET - opcode 0x65 1461 * 1462 */ 1463 static void 1464 init_reset(struct nvbios_init *init) 1465 { 1466 struct nvkm_bios *bios = init->bios; 1467 u32 reg = nvbios_rd32(bios, init->offset + 1); 1468 u32 data1 = nvbios_rd32(bios, init->offset + 5); 1469 u32 data2 = nvbios_rd32(bios, init->offset + 9); 1470 u32 savepci19; 1471 1472 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2); 1473 init->offset += 13; 1474 init_exec_force(init, true); 1475 1476 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000); 1477 init_wr32(init, reg, data1); 1478 udelay(10); 1479 init_wr32(init, reg, data2); 1480 init_wr32(init, 0x00184c, savepci19); 1481 init_mask(init, 0x001850, 0x00000001, 0x00000000); 1482 1483 init_exec_force(init, false); 1484 } 1485 1486 /** 1487 * INIT_CONFIGURE_MEM - opcode 0x66 1488 * 1489 */ 1490 static u16 1491 init_configure_mem_clk(struct nvbios_init *init) 1492 { 1493 u16 mdata = bmp_mem_init_table(init->bios); 1494 if (mdata) 1495 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66; 1496 return mdata; 1497 } 1498 1499 static void 1500 init_configure_mem(struct nvbios_init *init) 1501 { 1502 struct nvkm_bios *bios = init->bios; 1503 u16 mdata, sdata; 1504 u32 addr, data; 1505 1506 trace("CONFIGURE_MEM\n"); 1507 init->offset += 1; 1508 1509 if (bios->version.major > 2) { 1510 init_done(init); 1511 return; 1512 } 1513 init_exec_force(init, true); 1514 1515 mdata = init_configure_mem_clk(init); 1516 sdata = bmp_sdr_seq_table(bios); 1517 if (nvbios_rd08(bios, mdata) & 0x01) 1518 sdata = bmp_ddr_seq_table(bios); 1519 mdata += 6; /* skip to data */ 1520 1521 data = init_rdvgai(init, 0x03c4, 0x01); 1522 init_wrvgai(init, 0x03c4, 0x01, data | 0x20); 1523 1524 for (; (addr = nvbios_rd32(bios, sdata)) != 0xffffffff; sdata += 4) { 1525 switch (addr) { 1526 case 0x10021c: /* CKE_NORMAL */ 1527 case 0x1002d0: /* CMD_REFRESH */ 1528 case 0x1002d4: /* CMD_PRECHARGE */ 1529 data = 0x00000001; 1530 break; 1531 default: 1532 data = nvbios_rd32(bios, mdata); 1533 mdata += 4; 1534 if (data == 0xffffffff) 1535 continue; 1536 break; 1537 } 1538 1539 init_wr32(init, addr, data); 1540 } 1541 1542 init_exec_force(init, false); 1543 } 1544 1545 /** 1546 * INIT_CONFIGURE_CLK - opcode 0x67 1547 * 1548 */ 1549 static void 1550 init_configure_clk(struct nvbios_init *init) 1551 { 1552 struct nvkm_bios *bios = init->bios; 1553 u16 mdata, clock; 1554 1555 trace("CONFIGURE_CLK\n"); 1556 init->offset += 1; 1557 1558 if (bios->version.major > 2) { 1559 init_done(init); 1560 return; 1561 } 1562 init_exec_force(init, true); 1563 1564 mdata = init_configure_mem_clk(init); 1565 1566 /* NVPLL */ 1567 clock = nvbios_rd16(bios, mdata + 4) * 10; 1568 init_prog_pll(init, 0x680500, clock); 1569 1570 /* MPLL */ 1571 clock = nvbios_rd16(bios, mdata + 2) * 10; 1572 if (nvbios_rd08(bios, mdata) & 0x01) 1573 clock *= 2; 1574 init_prog_pll(init, 0x680504, clock); 1575 1576 init_exec_force(init, false); 1577 } 1578 1579 /** 1580 * INIT_CONFIGURE_PREINIT - opcode 0x68 1581 * 1582 */ 1583 static void 1584 init_configure_preinit(struct nvbios_init *init) 1585 { 1586 struct nvkm_bios *bios = init->bios; 1587 u32 strap; 1588 1589 trace("CONFIGURE_PREINIT\n"); 1590 init->offset += 1; 1591 1592 if (bios->version.major > 2) { 1593 init_done(init); 1594 return; 1595 } 1596 init_exec_force(init, true); 1597 1598 strap = init_rd32(init, 0x101000); 1599 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6); 1600 init_wrvgai(init, 0x03d4, 0x3c, strap); 1601 1602 init_exec_force(init, false); 1603 } 1604 1605 /** 1606 * INIT_IO - opcode 0x69 1607 * 1608 */ 1609 static void 1610 init_io(struct nvbios_init *init) 1611 { 1612 struct nvkm_bios *bios = init->bios; 1613 u16 port = nvbios_rd16(bios, init->offset + 1); 1614 u8 mask = nvbios_rd16(bios, init->offset + 3); 1615 u8 data = nvbios_rd16(bios, init->offset + 4); 1616 u8 value; 1617 1618 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data); 1619 init->offset += 5; 1620 1621 /* ummm.. yes.. should really figure out wtf this is and why it's 1622 * needed some day.. it's almost certainly wrong, but, it also 1623 * somehow makes things work... 1624 */ 1625 if (bios->subdev.device->card_type >= NV_50 && 1626 port == 0x03c3 && data == 0x01) { 1627 init_mask(init, 0x614100, 0xf0800000, 0x00800000); 1628 init_mask(init, 0x00e18c, 0x00020000, 0x00020000); 1629 init_mask(init, 0x614900, 0xf0800000, 0x00800000); 1630 init_mask(init, 0x000200, 0x40000000, 0x00000000); 1631 mdelay(10); 1632 init_mask(init, 0x00e18c, 0x00020000, 0x00000000); 1633 init_mask(init, 0x000200, 0x40000000, 0x40000000); 1634 init_wr32(init, 0x614100, 0x00800018); 1635 init_wr32(init, 0x614900, 0x00800018); 1636 mdelay(10); 1637 init_wr32(init, 0x614100, 0x10000018); 1638 init_wr32(init, 0x614900, 0x10000018); 1639 } 1640 1641 value = init_rdport(init, port) & mask; 1642 init_wrport(init, port, data | value); 1643 } 1644 1645 /** 1646 * INIT_SUB - opcode 0x6b 1647 * 1648 */ 1649 static void 1650 init_sub(struct nvbios_init *init) 1651 { 1652 struct nvkm_bios *bios = init->bios; 1653 u8 index = nvbios_rd08(bios, init->offset + 1); 1654 u16 addr, save; 1655 1656 trace("SUB\t0x%02x\n", index); 1657 1658 addr = init_script(bios, index); 1659 if (addr && init_exec(init)) { 1660 save = init->offset; 1661 init->offset = addr; 1662 if (nvbios_exec(init)) { 1663 error("error parsing sub-table\n"); 1664 return; 1665 } 1666 init->offset = save; 1667 } 1668 1669 init->offset += 2; 1670 } 1671 1672 /** 1673 * INIT_RAM_CONDITION - opcode 0x6d 1674 * 1675 */ 1676 static void 1677 init_ram_condition(struct nvbios_init *init) 1678 { 1679 struct nvkm_bios *bios = init->bios; 1680 u8 mask = nvbios_rd08(bios, init->offset + 1); 1681 u8 value = nvbios_rd08(bios, init->offset + 2); 1682 1683 trace("RAM_CONDITION\t" 1684 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value); 1685 init->offset += 3; 1686 1687 if ((init_rd32(init, 0x100000) & mask) != value) 1688 init_exec_set(init, false); 1689 } 1690 1691 /** 1692 * INIT_NV_REG - opcode 0x6e 1693 * 1694 */ 1695 static void 1696 init_nv_reg(struct nvbios_init *init) 1697 { 1698 struct nvkm_bios *bios = init->bios; 1699 u32 reg = nvbios_rd32(bios, init->offset + 1); 1700 u32 mask = nvbios_rd32(bios, init->offset + 5); 1701 u32 data = nvbios_rd32(bios, init->offset + 9); 1702 1703 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); 1704 init->offset += 13; 1705 1706 init_mask(init, reg, ~mask, data); 1707 } 1708 1709 /** 1710 * INIT_MACRO - opcode 0x6f 1711 * 1712 */ 1713 static void 1714 init_macro(struct nvbios_init *init) 1715 { 1716 struct nvkm_bios *bios = init->bios; 1717 u8 macro = nvbios_rd08(bios, init->offset + 1); 1718 u16 table; 1719 1720 trace("MACRO\t0x%02x\n", macro); 1721 1722 table = init_macro_table(init); 1723 if (table) { 1724 u32 addr = nvbios_rd32(bios, table + (macro * 8) + 0); 1725 u32 data = nvbios_rd32(bios, table + (macro * 8) + 4); 1726 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data); 1727 init_wr32(init, addr, data); 1728 } 1729 1730 init->offset += 2; 1731 } 1732 1733 /** 1734 * INIT_RESUME - opcode 0x72 1735 * 1736 */ 1737 static void 1738 init_resume(struct nvbios_init *init) 1739 { 1740 trace("RESUME\n"); 1741 init->offset += 1; 1742 init_exec_set(init, true); 1743 } 1744 1745 /** 1746 * INIT_STRAP_CONDITION - opcode 0x73 1747 * 1748 */ 1749 static void 1750 init_strap_condition(struct nvbios_init *init) 1751 { 1752 struct nvkm_bios *bios = init->bios; 1753 u32 mask = nvbios_rd32(bios, init->offset + 1); 1754 u32 value = nvbios_rd32(bios, init->offset + 5); 1755 1756 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value); 1757 init->offset += 9; 1758 1759 if ((init_rd32(init, 0x101000) & mask) != value) 1760 init_exec_set(init, false); 1761 } 1762 1763 /** 1764 * INIT_TIME - opcode 0x74 1765 * 1766 */ 1767 static void 1768 init_time(struct nvbios_init *init) 1769 { 1770 struct nvkm_bios *bios = init->bios; 1771 u16 usec = nvbios_rd16(bios, init->offset + 1); 1772 1773 trace("TIME\t0x%04x\n", usec); 1774 init->offset += 3; 1775 1776 if (init_exec(init)) { 1777 if (usec < 1000) 1778 udelay(usec); 1779 else 1780 mdelay((usec + 900) / 1000); 1781 } 1782 } 1783 1784 /** 1785 * INIT_CONDITION - opcode 0x75 1786 * 1787 */ 1788 static void 1789 init_condition(struct nvbios_init *init) 1790 { 1791 struct nvkm_bios *bios = init->bios; 1792 u8 cond = nvbios_rd08(bios, init->offset + 1); 1793 1794 trace("CONDITION\t0x%02x\n", cond); 1795 init->offset += 2; 1796 1797 if (!init_condition_met(init, cond)) 1798 init_exec_set(init, false); 1799 } 1800 1801 /** 1802 * INIT_IO_CONDITION - opcode 0x76 1803 * 1804 */ 1805 static void 1806 init_io_condition(struct nvbios_init *init) 1807 { 1808 struct nvkm_bios *bios = init->bios; 1809 u8 cond = nvbios_rd08(bios, init->offset + 1); 1810 1811 trace("IO_CONDITION\t0x%02x\n", cond); 1812 init->offset += 2; 1813 1814 if (!init_io_condition_met(init, cond)) 1815 init_exec_set(init, false); 1816 } 1817 1818 /** 1819 * INIT_ZM_REG16 - opcode 0x77 1820 * 1821 */ 1822 static void 1823 init_zm_reg16(struct nvbios_init *init) 1824 { 1825 struct nvkm_bios *bios = init->bios; 1826 u32 addr = nvbios_rd32(bios, init->offset + 1); 1827 u16 data = nvbios_rd16(bios, init->offset + 5); 1828 1829 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data); 1830 init->offset += 7; 1831 1832 init_wr32(init, addr, data); 1833 } 1834 1835 /** 1836 * INIT_INDEX_IO - opcode 0x78 1837 * 1838 */ 1839 static void 1840 init_index_io(struct nvbios_init *init) 1841 { 1842 struct nvkm_bios *bios = init->bios; 1843 u16 port = nvbios_rd16(bios, init->offset + 1); 1844 u8 index = nvbios_rd16(bios, init->offset + 3); 1845 u8 mask = nvbios_rd08(bios, init->offset + 4); 1846 u8 data = nvbios_rd08(bios, init->offset + 5); 1847 u8 value; 1848 1849 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n", 1850 port, index, mask, data); 1851 init->offset += 6; 1852 1853 value = init_rdvgai(init, port, index) & mask; 1854 init_wrvgai(init, port, index, data | value); 1855 } 1856 1857 /** 1858 * INIT_PLL - opcode 0x79 1859 * 1860 */ 1861 static void 1862 init_pll(struct nvbios_init *init) 1863 { 1864 struct nvkm_bios *bios = init->bios; 1865 u32 reg = nvbios_rd32(bios, init->offset + 1); 1866 u32 freq = nvbios_rd16(bios, init->offset + 5) * 10; 1867 1868 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 1869 init->offset += 7; 1870 1871 init_prog_pll(init, reg, freq); 1872 } 1873 1874 /** 1875 * INIT_ZM_REG - opcode 0x7a 1876 * 1877 */ 1878 static void 1879 init_zm_reg(struct nvbios_init *init) 1880 { 1881 struct nvkm_bios *bios = init->bios; 1882 u32 addr = nvbios_rd32(bios, init->offset + 1); 1883 u32 data = nvbios_rd32(bios, init->offset + 5); 1884 1885 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data); 1886 init->offset += 9; 1887 1888 if (addr == 0x000200) 1889 data |= 0x00000001; 1890 1891 init_wr32(init, addr, data); 1892 } 1893 1894 /** 1895 * INIT_RAM_RESTRICT_PLL - opcde 0x87 1896 * 1897 */ 1898 static void 1899 init_ram_restrict_pll(struct nvbios_init *init) 1900 { 1901 struct nvkm_bios *bios = init->bios; 1902 u8 type = nvbios_rd08(bios, init->offset + 1); 1903 u8 count = init_ram_restrict_group_count(init); 1904 u8 strap = init_ram_restrict(init); 1905 u8 cconf; 1906 1907 trace("RAM_RESTRICT_PLL\t0x%02x\n", type); 1908 init->offset += 2; 1909 1910 for (cconf = 0; cconf < count; cconf++) { 1911 u32 freq = nvbios_rd32(bios, init->offset); 1912 1913 if (cconf == strap) { 1914 trace("%dkHz *\n", freq); 1915 init_prog_pll(init, type, freq); 1916 } else { 1917 trace("%dkHz\n", freq); 1918 } 1919 1920 init->offset += 4; 1921 } 1922 } 1923 1924 /** 1925 * INIT_GPIO - opcode 0x8e 1926 * 1927 */ 1928 static void 1929 init_gpio(struct nvbios_init *init) 1930 { 1931 struct nvkm_gpio *gpio = init->bios->subdev.device->gpio; 1932 1933 trace("GPIO\n"); 1934 init->offset += 1; 1935 1936 if (init_exec(init)) 1937 nvkm_gpio_reset(gpio, DCB_GPIO_UNUSED); 1938 } 1939 1940 /** 1941 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f 1942 * 1943 */ 1944 static void 1945 init_ram_restrict_zm_reg_group(struct nvbios_init *init) 1946 { 1947 struct nvkm_bios *bios = init->bios; 1948 u32 addr = nvbios_rd32(bios, init->offset + 1); 1949 u8 incr = nvbios_rd08(bios, init->offset + 5); 1950 u8 num = nvbios_rd08(bios, init->offset + 6); 1951 u8 count = init_ram_restrict_group_count(init); 1952 u8 index = init_ram_restrict(init); 1953 u8 i, j; 1954 1955 trace("RAM_RESTRICT_ZM_REG_GROUP\t" 1956 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num); 1957 init->offset += 7; 1958 1959 for (i = 0; i < num; i++) { 1960 trace("\tR[0x%06x] = {\n", addr); 1961 for (j = 0; j < count; j++) { 1962 u32 data = nvbios_rd32(bios, init->offset); 1963 1964 if (j == index) { 1965 trace("\t\t0x%08x *\n", data); 1966 init_wr32(init, addr, data); 1967 } else { 1968 trace("\t\t0x%08x\n", data); 1969 } 1970 1971 init->offset += 4; 1972 } 1973 trace("\t}\n"); 1974 addr += incr; 1975 } 1976 } 1977 1978 /** 1979 * INIT_COPY_ZM_REG - opcode 0x90 1980 * 1981 */ 1982 static void 1983 init_copy_zm_reg(struct nvbios_init *init) 1984 { 1985 struct nvkm_bios *bios = init->bios; 1986 u32 sreg = nvbios_rd32(bios, init->offset + 1); 1987 u32 dreg = nvbios_rd32(bios, init->offset + 5); 1988 1989 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg); 1990 init->offset += 9; 1991 1992 init_wr32(init, dreg, init_rd32(init, sreg)); 1993 } 1994 1995 /** 1996 * INIT_ZM_REG_GROUP - opcode 0x91 1997 * 1998 */ 1999 static void 2000 init_zm_reg_group(struct nvbios_init *init) 2001 { 2002 struct nvkm_bios *bios = init->bios; 2003 u32 addr = nvbios_rd32(bios, init->offset + 1); 2004 u8 count = nvbios_rd08(bios, init->offset + 5); 2005 2006 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr); 2007 init->offset += 6; 2008 2009 while (count--) { 2010 u32 data = nvbios_rd32(bios, init->offset); 2011 trace("\t0x%08x\n", data); 2012 init_wr32(init, addr, data); 2013 init->offset += 4; 2014 } 2015 } 2016 2017 /** 2018 * INIT_XLAT - opcode 0x96 2019 * 2020 */ 2021 static void 2022 init_xlat(struct nvbios_init *init) 2023 { 2024 struct nvkm_bios *bios = init->bios; 2025 u32 saddr = nvbios_rd32(bios, init->offset + 1); 2026 u8 sshift = nvbios_rd08(bios, init->offset + 5); 2027 u8 smask = nvbios_rd08(bios, init->offset + 6); 2028 u8 index = nvbios_rd08(bios, init->offset + 7); 2029 u32 daddr = nvbios_rd32(bios, init->offset + 8); 2030 u32 dmask = nvbios_rd32(bios, init->offset + 12); 2031 u8 shift = nvbios_rd08(bios, init->offset + 16); 2032 u32 data; 2033 2034 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= " 2035 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n", 2036 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>", 2037 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift); 2038 init->offset += 17; 2039 2040 data = init_shift(init_rd32(init, saddr), sshift) & smask; 2041 data = init_xlat_(init, index, data) << shift; 2042 init_mask(init, daddr, ~dmask, data); 2043 } 2044 2045 /** 2046 * INIT_ZM_MASK_ADD - opcode 0x97 2047 * 2048 */ 2049 static void 2050 init_zm_mask_add(struct nvbios_init *init) 2051 { 2052 struct nvkm_bios *bios = init->bios; 2053 u32 addr = nvbios_rd32(bios, init->offset + 1); 2054 u32 mask = nvbios_rd32(bios, init->offset + 5); 2055 u32 add = nvbios_rd32(bios, init->offset + 9); 2056 u32 data; 2057 2058 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); 2059 init->offset += 13; 2060 2061 data = init_rd32(init, addr); 2062 data = (data & mask) | ((data + add) & ~mask); 2063 init_wr32(init, addr, data); 2064 } 2065 2066 /** 2067 * INIT_AUXCH - opcode 0x98 2068 * 2069 */ 2070 static void 2071 init_auxch(struct nvbios_init *init) 2072 { 2073 struct nvkm_bios *bios = init->bios; 2074 u32 addr = nvbios_rd32(bios, init->offset + 1); 2075 u8 count = nvbios_rd08(bios, init->offset + 5); 2076 2077 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2078 init->offset += 6; 2079 2080 while (count--) { 2081 u8 mask = nvbios_rd08(bios, init->offset + 0); 2082 u8 data = nvbios_rd08(bios, init->offset + 1); 2083 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 2084 mask = init_rdauxr(init, addr) & mask; 2085 init_wrauxr(init, addr, mask | data); 2086 init->offset += 2; 2087 } 2088 } 2089 2090 /** 2091 * INIT_AUXCH - opcode 0x99 2092 * 2093 */ 2094 static void 2095 init_zm_auxch(struct nvbios_init *init) 2096 { 2097 struct nvkm_bios *bios = init->bios; 2098 u32 addr = nvbios_rd32(bios, init->offset + 1); 2099 u8 count = nvbios_rd08(bios, init->offset + 5); 2100 2101 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2102 init->offset += 6; 2103 2104 while (count--) { 2105 u8 data = nvbios_rd08(bios, init->offset + 0); 2106 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data); 2107 init_wrauxr(init, addr, data); 2108 init->offset += 1; 2109 } 2110 } 2111 2112 /** 2113 * INIT_I2C_LONG_IF - opcode 0x9a 2114 * 2115 */ 2116 static void 2117 init_i2c_long_if(struct nvbios_init *init) 2118 { 2119 struct nvkm_bios *bios = init->bios; 2120 u8 index = nvbios_rd08(bios, init->offset + 1); 2121 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 2122 u8 reglo = nvbios_rd08(bios, init->offset + 3); 2123 u8 reghi = nvbios_rd08(bios, init->offset + 4); 2124 u8 mask = nvbios_rd08(bios, init->offset + 5); 2125 u8 data = nvbios_rd08(bios, init->offset + 6); 2126 struct i2c_adapter *adap; 2127 2128 trace("I2C_LONG_IF\t" 2129 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n", 2130 index, addr, reglo, reghi, mask, data); 2131 init->offset += 7; 2132 2133 adap = init_i2c(init, index); 2134 if (adap) { 2135 u8 i[2] = { reghi, reglo }; 2136 u8 o[1] = {}; 2137 struct i2c_msg msg[] = { 2138 { .addr = addr, .flags = 0, .len = 2, .buf = i }, 2139 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o } 2140 }; 2141 int ret; 2142 2143 ret = i2c_transfer(adap, msg, 2); 2144 if (ret == 2 && ((o[0] & mask) == data)) 2145 return; 2146 } 2147 2148 init_exec_set(init, false); 2149 } 2150 2151 /** 2152 * INIT_GPIO_NE - opcode 0xa9 2153 * 2154 */ 2155 static void 2156 init_gpio_ne(struct nvbios_init *init) 2157 { 2158 struct nvkm_bios *bios = init->bios; 2159 struct nvkm_gpio *gpio = bios->subdev.device->gpio; 2160 struct dcb_gpio_func func; 2161 u8 count = nvbios_rd08(bios, init->offset + 1); 2162 u8 idx = 0, ver, len; 2163 u16 data, i; 2164 2165 trace("GPIO_NE\t"); 2166 init->offset += 2; 2167 2168 for (i = init->offset; i < init->offset + count; i++) 2169 cont("0x%02x ", nvbios_rd08(bios, i)); 2170 cont("\n"); 2171 2172 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) { 2173 if (func.func != DCB_GPIO_UNUSED) { 2174 for (i = init->offset; i < init->offset + count; i++) { 2175 if (func.func == nvbios_rd08(bios, i)) 2176 break; 2177 } 2178 2179 trace("\tFUNC[0x%02x]", func.func); 2180 if (i == (init->offset + count)) { 2181 cont(" *"); 2182 if (init_exec(init)) 2183 nvkm_gpio_reset(gpio, func.func); 2184 } 2185 cont("\n"); 2186 } 2187 } 2188 2189 init->offset += count; 2190 } 2191 2192 static struct nvbios_init_opcode { 2193 void (*exec)(struct nvbios_init *); 2194 } init_opcode[] = { 2195 [0x32] = { init_io_restrict_prog }, 2196 [0x33] = { init_repeat }, 2197 [0x34] = { init_io_restrict_pll }, 2198 [0x36] = { init_end_repeat }, 2199 [0x37] = { init_copy }, 2200 [0x38] = { init_not }, 2201 [0x39] = { init_io_flag_condition }, 2202 [0x3a] = { init_dp_condition }, 2203 [0x3b] = { init_io_mask_or }, 2204 [0x3c] = { init_io_or }, 2205 [0x47] = { init_andn_reg }, 2206 [0x48] = { init_or_reg }, 2207 [0x49] = { init_idx_addr_latched }, 2208 [0x4a] = { init_io_restrict_pll2 }, 2209 [0x4b] = { init_pll2 }, 2210 [0x4c] = { init_i2c_byte }, 2211 [0x4d] = { init_zm_i2c_byte }, 2212 [0x4e] = { init_zm_i2c }, 2213 [0x4f] = { init_tmds }, 2214 [0x50] = { init_zm_tmds_group }, 2215 [0x51] = { init_cr_idx_adr_latch }, 2216 [0x52] = { init_cr }, 2217 [0x53] = { init_zm_cr }, 2218 [0x54] = { init_zm_cr_group }, 2219 [0x56] = { init_condition_time }, 2220 [0x57] = { init_ltime }, 2221 [0x58] = { init_zm_reg_sequence }, 2222 [0x59] = { init_pll_indirect }, 2223 [0x5a] = { init_zm_reg_indirect }, 2224 [0x5b] = { init_sub_direct }, 2225 [0x5c] = { init_jump }, 2226 [0x5e] = { init_i2c_if }, 2227 [0x5f] = { init_copy_nv_reg }, 2228 [0x62] = { init_zm_index_io }, 2229 [0x63] = { init_compute_mem }, 2230 [0x65] = { init_reset }, 2231 [0x66] = { init_configure_mem }, 2232 [0x67] = { init_configure_clk }, 2233 [0x68] = { init_configure_preinit }, 2234 [0x69] = { init_io }, 2235 [0x6b] = { init_sub }, 2236 [0x6d] = { init_ram_condition }, 2237 [0x6e] = { init_nv_reg }, 2238 [0x6f] = { init_macro }, 2239 [0x71] = { init_done }, 2240 [0x72] = { init_resume }, 2241 [0x73] = { init_strap_condition }, 2242 [0x74] = { init_time }, 2243 [0x75] = { init_condition }, 2244 [0x76] = { init_io_condition }, 2245 [0x77] = { init_zm_reg16 }, 2246 [0x78] = { init_index_io }, 2247 [0x79] = { init_pll }, 2248 [0x7a] = { init_zm_reg }, 2249 [0x87] = { init_ram_restrict_pll }, 2250 [0x8c] = { init_reserved }, 2251 [0x8d] = { init_reserved }, 2252 [0x8e] = { init_gpio }, 2253 [0x8f] = { init_ram_restrict_zm_reg_group }, 2254 [0x90] = { init_copy_zm_reg }, 2255 [0x91] = { init_zm_reg_group }, 2256 [0x92] = { init_reserved }, 2257 [0x96] = { init_xlat }, 2258 [0x97] = { init_zm_mask_add }, 2259 [0x98] = { init_auxch }, 2260 [0x99] = { init_zm_auxch }, 2261 [0x9a] = { init_i2c_long_if }, 2262 [0xa9] = { init_gpio_ne }, 2263 [0xaa] = { init_reserved }, 2264 }; 2265 2266 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0])) 2267 2268 int 2269 nvbios_exec(struct nvbios_init *init) 2270 { 2271 init->nested++; 2272 while (init->offset) { 2273 u8 opcode = nvbios_rd08(init->bios, init->offset); 2274 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) { 2275 error("unknown opcode 0x%02x\n", opcode); 2276 return -EINVAL; 2277 } 2278 2279 init_opcode[opcode].exec(init); 2280 } 2281 init->nested--; 2282 return 0; 2283 } 2284 2285 int 2286 nvbios_init(struct nvkm_subdev *subdev, bool execute) 2287 { 2288 struct nvkm_bios *bios = subdev->device->bios; 2289 int ret = 0; 2290 int i = -1; 2291 u16 data; 2292 2293 if (execute) 2294 nvkm_debug(subdev, "running init tables\n"); 2295 while (!ret && (data = (init_script(bios, ++i)))) { 2296 struct nvbios_init init = { 2297 .subdev = subdev, 2298 .bios = bios, 2299 .offset = data, 2300 .outp = NULL, 2301 .crtc = -1, 2302 .execute = execute ? 1 : 0, 2303 }; 2304 2305 ret = nvbios_exec(&init); 2306 } 2307 2308 /* the vbios parser will run this right after the normal init 2309 * tables, whereas the binary driver appears to run it later. 2310 */ 2311 if (!ret && (data = init_unknown_script(bios))) { 2312 struct nvbios_init init = { 2313 .subdev = subdev, 2314 .bios = bios, 2315 .offset = data, 2316 .outp = NULL, 2317 .crtc = -1, 2318 .execute = execute ? 1 : 0, 2319 }; 2320 2321 ret = nvbios_exec(&init); 2322 } 2323 2324 return ret; 2325 } 2326