1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 26 #include <core/gpuobj.h> 27 #include <subdev/fb.h> 28 #include <subdev/mmu.h> 29 #include <subdev/timer.h> 30 31 struct nvkm_vm * 32 nv50_bar_kmap(struct nvkm_bar *base) 33 { 34 return nv50_bar(base)->bar3_vm; 35 } 36 37 int 38 nv50_bar_umap(struct nvkm_bar *base, u64 size, int type, struct nvkm_vma *vma) 39 { 40 struct nv50_bar *bar = nv50_bar(base); 41 return nvkm_vm_get(bar->bar1_vm, size, type, NV_MEM_ACCESS_RW, vma); 42 } 43 44 static void 45 nv50_bar_flush(struct nvkm_bar *base) 46 { 47 struct nv50_bar *bar = nv50_bar(base); 48 struct nvkm_device *device = bar->base.subdev.device; 49 unsigned long flags; 50 spin_lock_irqsave(&bar->base.lock, flags); 51 nvkm_wr32(device, 0x00330c, 0x00000001); 52 nvkm_msec(device, 2000, 53 if (!(nvkm_rd32(device, 0x00330c) & 0x00000002)) 54 break; 55 ); 56 spin_unlock_irqrestore(&bar->base.lock, flags); 57 } 58 59 int 60 nv50_bar_oneinit(struct nvkm_bar *base) 61 { 62 struct nv50_bar *bar = nv50_bar(base); 63 struct nvkm_device *device = bar->base.subdev.device; 64 static struct lock_class_key bar1_lock; 65 static struct lock_class_key bar3_lock; 66 struct nvkm_vm *vm; 67 u64 start, limit; 68 int ret; 69 70 ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem); 71 if (ret) 72 return ret; 73 74 ret = nvkm_gpuobj_new(device, bar->pgd_addr, 0, false, bar->mem, 75 &bar->pad); 76 if (ret) 77 return ret; 78 79 ret = nvkm_gpuobj_new(device, 0x4000, 0, false, bar->mem, &bar->pgd); 80 if (ret) 81 return ret; 82 83 /* BAR3 */ 84 start = 0x0100000000ULL; 85 limit = start + nv_device_resource_len(device, 3); 86 87 ret = nvkm_vm_new(device, start, limit, start, &bar3_lock, &vm); 88 if (ret) 89 return ret; 90 91 atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); 92 93 ret = nvkm_vm_boot(vm, limit-- - start); 94 if (ret) 95 return ret; 96 97 ret = nvkm_vm_ref(vm, &bar->bar3_vm, bar->pgd); 98 nvkm_vm_ref(NULL, &vm, NULL); 99 if (ret) 100 return ret; 101 102 ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar3); 103 if (ret) 104 return ret; 105 106 nvkm_kmap(bar->bar3); 107 nvkm_wo32(bar->bar3, 0x00, 0x7fc00000); 108 nvkm_wo32(bar->bar3, 0x04, lower_32_bits(limit)); 109 nvkm_wo32(bar->bar3, 0x08, lower_32_bits(start)); 110 nvkm_wo32(bar->bar3, 0x0c, upper_32_bits(limit) << 24 | 111 upper_32_bits(start)); 112 nvkm_wo32(bar->bar3, 0x10, 0x00000000); 113 nvkm_wo32(bar->bar3, 0x14, 0x00000000); 114 nvkm_done(bar->bar3); 115 116 /* BAR1 */ 117 start = 0x0000000000ULL; 118 limit = start + nv_device_resource_len(device, 1); 119 120 ret = nvkm_vm_new(device, start, limit--, start, &bar1_lock, &vm); 121 if (ret) 122 return ret; 123 124 atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); 125 126 ret = nvkm_vm_ref(vm, &bar->bar1_vm, bar->pgd); 127 nvkm_vm_ref(NULL, &vm, NULL); 128 if (ret) 129 return ret; 130 131 ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1); 132 if (ret) 133 return ret; 134 135 nvkm_kmap(bar->bar1); 136 nvkm_wo32(bar->bar1, 0x00, 0x7fc00000); 137 nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit)); 138 nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start)); 139 nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 | 140 upper_32_bits(start)); 141 nvkm_wo32(bar->bar1, 0x10, 0x00000000); 142 nvkm_wo32(bar->bar1, 0x14, 0x00000000); 143 nvkm_done(bar->bar1); 144 return 0; 145 } 146 147 int 148 nv50_bar_init(struct nvkm_bar *base) 149 { 150 struct nv50_bar *bar = nv50_bar(base); 151 struct nvkm_device *device = bar->base.subdev.device; 152 int i; 153 154 nvkm_mask(device, 0x000200, 0x00000100, 0x00000000); 155 nvkm_mask(device, 0x000200, 0x00000100, 0x00000100); 156 nvkm_wr32(device, 0x100c80, 0x00060001); 157 if (nvkm_msec(device, 2000, 158 if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) 159 break; 160 ) < 0) 161 return -EBUSY; 162 163 nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12); 164 nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12); 165 nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4); 166 nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar3->node->offset >> 4); 167 for (i = 0; i < 8; i++) 168 nvkm_wr32(device, 0x001900 + (i * 4), 0x00000000); 169 return 0; 170 } 171 172 void * 173 nv50_bar_dtor(struct nvkm_bar *base) 174 { 175 struct nv50_bar *bar = nv50_bar(base); 176 nvkm_gpuobj_del(&bar->bar1); 177 nvkm_vm_ref(NULL, &bar->bar1_vm, bar->pgd); 178 nvkm_gpuobj_del(&bar->bar3); 179 if (bar->bar3_vm) { 180 nvkm_memory_del(&bar->bar3_vm->pgt[0].mem[0]); 181 nvkm_vm_ref(NULL, &bar->bar3_vm, bar->pgd); 182 } 183 nvkm_gpuobj_del(&bar->pgd); 184 nvkm_gpuobj_del(&bar->pad); 185 nvkm_gpuobj_del(&bar->mem); 186 return bar; 187 } 188 189 int 190 nv50_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device, 191 int index, u32 pgd_addr, struct nvkm_bar **pbar) 192 { 193 struct nv50_bar *bar; 194 if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL))) 195 return -ENOMEM; 196 nvkm_bar_ctor(func, device, index, &bar->base); 197 bar->pgd_addr = pgd_addr; 198 *pbar = &bar->base; 199 return 0; 200 } 201 202 static const struct nvkm_bar_func 203 nv50_bar_func = { 204 .dtor = nv50_bar_dtor, 205 .oneinit = nv50_bar_oneinit, 206 .init = nv50_bar_init, 207 .kmap = nv50_bar_kmap, 208 .umap = nv50_bar_umap, 209 .flush = nv50_bar_flush, 210 }; 211 212 int 213 nv50_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) 214 { 215 return nv50_bar_new_(&nv50_bar_func, device, index, 0x1400, pbar); 216 } 217