1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 26 #include <core/gpuobj.h> 27 #include <subdev/fb.h> 28 #include <subdev/mmu.h> 29 30 struct gf100_bar_vm { 31 struct nvkm_gpuobj *mem; 32 struct nvkm_gpuobj *pgd; 33 struct nvkm_vm *vm; 34 }; 35 36 struct gf100_bar { 37 struct nvkm_bar base; 38 spinlock_t lock; 39 struct gf100_bar_vm bar[2]; 40 }; 41 42 static int 43 gf100_bar_kmap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags, 44 struct nvkm_vma *vma) 45 { 46 struct gf100_bar *bar = container_of(obj, typeof(*bar), base); 47 int ret; 48 49 ret = nvkm_vm_get(bar->bar[0].vm, mem->size << 12, 12, flags, vma); 50 if (ret) 51 return ret; 52 53 nvkm_vm_map(vma, mem); 54 return 0; 55 } 56 57 static int 58 gf100_bar_umap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags, 59 struct nvkm_vma *vma) 60 { 61 struct gf100_bar *bar = container_of(obj, typeof(*bar), base); 62 int ret; 63 64 ret = nvkm_vm_get(bar->bar[1].vm, mem->size << 12, 65 mem->page_shift, flags, vma); 66 if (ret) 67 return ret; 68 69 nvkm_vm_map(vma, mem); 70 return 0; 71 } 72 73 static void 74 gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma) 75 { 76 nvkm_vm_unmap(vma); 77 nvkm_vm_put(vma); 78 } 79 80 static int 81 gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm, 82 int bar_nr) 83 { 84 struct nvkm_device *device = nv_device(&bar->base); 85 struct nvkm_vm *vm; 86 resource_size_t bar_len; 87 int ret; 88 89 ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x1000, 0, 0, 90 &bar_vm->mem); 91 if (ret) 92 return ret; 93 94 ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x8000, 0, 0, 95 &bar_vm->pgd); 96 if (ret) 97 return ret; 98 99 bar_len = nv_device_resource_len(device, bar_nr); 100 101 ret = nvkm_vm_new(device, 0, bar_len, 0, &vm); 102 if (ret) 103 return ret; 104 105 atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); 106 107 /* 108 * Bootstrap page table lookup. 109 */ 110 if (bar_nr == 3) { 111 ret = nvkm_gpuobj_new(nv_object(bar), NULL, 112 (bar_len >> 12) * 8, 0x1000, 113 NVOBJ_FLAG_ZERO_ALLOC, 114 &vm->pgt[0].obj[0]); 115 vm->pgt[0].refcount[0] = 1; 116 if (ret) 117 return ret; 118 } 119 120 ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd); 121 nvkm_vm_ref(NULL, &vm, NULL); 122 if (ret) 123 return ret; 124 125 nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); 126 nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); 127 nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); 128 nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); 129 return 0; 130 } 131 132 int 133 gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 134 struct nvkm_oclass *oclass, void *data, u32 size, 135 struct nvkm_object **pobject) 136 { 137 struct nvkm_device *device = nv_device(parent); 138 struct gf100_bar *bar; 139 bool has_bar3 = nv_device_resource_len(device, 3) != 0; 140 int ret; 141 142 ret = nvkm_bar_create(parent, engine, oclass, &bar); 143 *pobject = nv_object(bar); 144 if (ret) 145 return ret; 146 147 /* BAR3 */ 148 if (has_bar3) { 149 ret = gf100_bar_ctor_vm(bar, &bar->bar[0], 3); 150 if (ret) 151 return ret; 152 } 153 154 /* BAR1 */ 155 ret = gf100_bar_ctor_vm(bar, &bar->bar[1], 1); 156 if (ret) 157 return ret; 158 159 if (has_bar3) { 160 bar->base.alloc = nvkm_bar_alloc; 161 bar->base.kmap = gf100_bar_kmap; 162 } 163 bar->base.umap = gf100_bar_umap; 164 bar->base.unmap = gf100_bar_unmap; 165 bar->base.flush = g84_bar_flush; 166 spin_lock_init(&bar->lock); 167 return 0; 168 } 169 170 void 171 gf100_bar_dtor(struct nvkm_object *object) 172 { 173 struct gf100_bar *bar = (void *)object; 174 175 nvkm_vm_ref(NULL, &bar->bar[1].vm, bar->bar[1].pgd); 176 nvkm_gpuobj_ref(NULL, &bar->bar[1].pgd); 177 nvkm_gpuobj_ref(NULL, &bar->bar[1].mem); 178 179 if (bar->bar[0].vm) { 180 nvkm_gpuobj_ref(NULL, &bar->bar[0].vm->pgt[0].obj[0]); 181 nvkm_vm_ref(NULL, &bar->bar[0].vm, bar->bar[0].pgd); 182 } 183 nvkm_gpuobj_ref(NULL, &bar->bar[0].pgd); 184 nvkm_gpuobj_ref(NULL, &bar->bar[0].mem); 185 186 nvkm_bar_destroy(&bar->base); 187 } 188 189 int 190 gf100_bar_init(struct nvkm_object *object) 191 { 192 struct gf100_bar *bar = (void *)object; 193 int ret; 194 195 ret = nvkm_bar_init(&bar->base); 196 if (ret) 197 return ret; 198 199 nv_mask(bar, 0x000200, 0x00000100, 0x00000000); 200 nv_mask(bar, 0x000200, 0x00000100, 0x00000100); 201 202 nv_wr32(bar, 0x001704, 0x80000000 | bar->bar[1].mem->addr >> 12); 203 if (bar->bar[0].mem) 204 nv_wr32(bar, 0x001714, 205 0xc0000000 | bar->bar[0].mem->addr >> 12); 206 return 0; 207 } 208 209 struct nvkm_oclass 210 gf100_bar_oclass = { 211 .handle = NV_SUBDEV(BAR, 0xc0), 212 .ofuncs = &(struct nvkm_ofuncs) { 213 .ctor = gf100_bar_ctor, 214 .dtor = gf100_bar_dtor, 215 .init = gf100_bar_init, 216 .fini = _nvkm_bar_fini, 217 }, 218 }; 219