1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 26 #include <core/gpuobj.h> 27 #include <subdev/fb.h> 28 #include <subdev/mmu.h> 29 30 struct gf100_bar_vm { 31 struct nvkm_memory *mem; 32 struct nvkm_gpuobj *pgd; 33 struct nvkm_vm *vm; 34 }; 35 36 struct gf100_bar { 37 struct nvkm_bar base; 38 spinlock_t lock; 39 struct gf100_bar_vm bar[2]; 40 }; 41 42 static struct nvkm_vm * 43 gf100_bar_kmap(struct nvkm_bar *obj) 44 { 45 struct gf100_bar *bar = container_of(obj, typeof(*bar), base); 46 return bar->bar[0].vm; 47 } 48 49 static int 50 gf100_bar_umap(struct nvkm_bar *obj, u64 size, int type, struct nvkm_vma *vma) 51 { 52 struct gf100_bar *bar = container_of(obj, typeof(*bar), base); 53 return nvkm_vm_get(bar->bar[1].vm, size, type, NV_MEM_ACCESS_RW, vma); 54 } 55 56 static void 57 gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma) 58 { 59 nvkm_vm_unmap(vma); 60 nvkm_vm_put(vma); 61 } 62 63 64 static int 65 gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm, 66 struct lock_class_key *key, int bar_nr) 67 { 68 struct nvkm_device *device = nv_device(&bar->base); 69 struct nvkm_vm *vm; 70 resource_size_t bar_len; 71 int ret; 72 73 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0, false, 74 &bar_vm->mem); 75 if (ret) 76 return ret; 77 78 ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x8000, 0, 0, 79 &bar_vm->pgd); 80 if (ret) 81 return ret; 82 83 bar_len = nv_device_resource_len(device, bar_nr); 84 85 ret = nvkm_vm_new(device, 0, bar_len, 0, key, &vm); 86 if (ret) 87 return ret; 88 89 atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); 90 91 /* 92 * Bootstrap page table lookup. 93 */ 94 if (bar_nr == 3) { 95 ret = nvkm_vm_boot(vm, bar_len); 96 if (ret) 97 return ret; 98 } 99 100 ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd); 101 nvkm_vm_ref(NULL, &vm, NULL); 102 if (ret) 103 return ret; 104 105 nvkm_kmap(bar_vm->mem); 106 nvkm_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); 107 nvkm_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); 108 nvkm_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); 109 nvkm_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); 110 nvkm_done(bar_vm->mem); 111 return 0; 112 } 113 114 int 115 gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 116 struct nvkm_oclass *oclass, void *data, u32 size, 117 struct nvkm_object **pobject) 118 { 119 static struct lock_class_key bar1_lock; 120 static struct lock_class_key bar3_lock; 121 struct nvkm_device *device = nv_device(parent); 122 struct gf100_bar *bar; 123 bool has_bar3 = nv_device_resource_len(device, 3) != 0; 124 int ret; 125 126 ret = nvkm_bar_create(parent, engine, oclass, &bar); 127 *pobject = nv_object(bar); 128 if (ret) 129 return ret; 130 131 device->bar = &bar->base; 132 bar->base.flush = g84_bar_flush; 133 spin_lock_init(&bar->lock); 134 135 /* BAR3 */ 136 if (has_bar3) { 137 ret = gf100_bar_ctor_vm(bar, &bar->bar[0], &bar3_lock, 3); 138 if (ret) 139 return ret; 140 } 141 142 /* BAR1 */ 143 ret = gf100_bar_ctor_vm(bar, &bar->bar[1], &bar1_lock, 1); 144 if (ret) 145 return ret; 146 147 if (has_bar3) 148 bar->base.kmap = gf100_bar_kmap; 149 bar->base.umap = gf100_bar_umap; 150 bar->base.unmap = gf100_bar_unmap; 151 return 0; 152 } 153 154 void 155 gf100_bar_dtor(struct nvkm_object *object) 156 { 157 struct gf100_bar *bar = (void *)object; 158 159 nvkm_vm_ref(NULL, &bar->bar[1].vm, bar->bar[1].pgd); 160 nvkm_gpuobj_ref(NULL, &bar->bar[1].pgd); 161 nvkm_memory_del(&bar->bar[1].mem); 162 163 if (bar->bar[0].vm) { 164 nvkm_memory_del(&bar->bar[0].vm->pgt[0].mem[0]); 165 nvkm_vm_ref(NULL, &bar->bar[0].vm, bar->bar[0].pgd); 166 } 167 nvkm_gpuobj_ref(NULL, &bar->bar[0].pgd); 168 nvkm_memory_del(&bar->bar[0].mem); 169 170 nvkm_bar_destroy(&bar->base); 171 } 172 173 int 174 gf100_bar_init(struct nvkm_object *object) 175 { 176 struct gf100_bar *bar = (void *)object; 177 struct nvkm_device *device = bar->base.subdev.device; 178 u32 addr; 179 int ret; 180 181 ret = nvkm_bar_init(&bar->base); 182 if (ret) 183 return ret; 184 185 nvkm_mask(device, 0x000200, 0x00000100, 0x00000000); 186 nvkm_mask(device, 0x000200, 0x00000100, 0x00000100); 187 188 addr = nvkm_memory_addr(bar->bar[1].mem) >> 12; 189 nvkm_wr32(device, 0x001704, 0x80000000 | addr); 190 191 if (bar->bar[0].mem) { 192 addr = nvkm_memory_addr(bar->bar[0].mem) >> 12; 193 nvkm_wr32(device, 0x001714, 0xc0000000 | addr); 194 } 195 196 return 0; 197 } 198 199 struct nvkm_oclass 200 gf100_bar_oclass = { 201 .handle = NV_SUBDEV(BAR, 0xc0), 202 .ofuncs = &(struct nvkm_ofuncs) { 203 .ctor = gf100_bar_ctor, 204 .dtor = gf100_bar_dtor, 205 .init = gf100_bar_init, 206 .fini = _nvkm_bar_fini, 207 }, 208 }; 209