1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gf100.h" 25 26 #include <core/gpuobj.h> 27 #include <core/option.h> 28 #include <subdev/fb.h> 29 #include <subdev/mmu.h> 30 31 struct nvkm_vmm * 32 gf100_bar_bar1_vmm(struct nvkm_bar *base) 33 { 34 return gf100_bar(base)->bar[1].vm; 35 } 36 37 void 38 gf100_bar_bar1_wait(struct nvkm_bar *base) 39 { 40 /* NFI why it's twice. */ 41 nvkm_bar_flush(base); 42 nvkm_bar_flush(base); 43 } 44 45 void 46 gf100_bar_bar1_fini(struct nvkm_bar *bar) 47 { 48 nvkm_mask(bar->subdev.device, 0x001704, 0x80000000, 0x00000000); 49 } 50 51 void 52 gf100_bar_bar1_init(struct nvkm_bar *base) 53 { 54 struct nvkm_device *device = base->subdev.device; 55 struct gf100_bar *bar = gf100_bar(base); 56 const u32 addr = nvkm_memory_addr(bar->bar[1].mem) >> 12; 57 nvkm_wr32(device, 0x001704, 0x80000000 | addr); 58 } 59 60 struct nvkm_vmm * 61 gf100_bar_bar2_vmm(struct nvkm_bar *base) 62 { 63 return gf100_bar(base)->bar[0].vm; 64 } 65 66 void 67 gf100_bar_bar2_fini(struct nvkm_bar *bar) 68 { 69 nvkm_mask(bar->subdev.device, 0x001714, 0x80000000, 0x00000000); 70 } 71 72 void 73 gf100_bar_bar2_init(struct nvkm_bar *base) 74 { 75 struct nvkm_device *device = base->subdev.device; 76 struct gf100_bar *bar = gf100_bar(base); 77 u32 addr = nvkm_memory_addr(bar->bar[0].mem) >> 12; 78 if (bar->bar2_halve) 79 addr |= 0x40000000; 80 nvkm_wr32(device, 0x001714, 0x80000000 | addr); 81 } 82 83 static int 84 gf100_bar_oneinit_bar(struct gf100_bar *bar, struct gf100_barN *bar_vm, 85 struct lock_class_key *key, int bar_nr) 86 { 87 struct nvkm_device *device = bar->base.subdev.device; 88 struct nvkm_vm *vm; 89 resource_size_t bar_len; 90 int ret; 91 92 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0, false, 93 &bar_vm->mem); 94 if (ret) 95 return ret; 96 97 ret = nvkm_gpuobj_new(device, 0x8000, 0, false, NULL, &bar_vm->pgd); 98 if (ret) 99 return ret; 100 101 bar_len = device->func->resource_size(device, bar_nr); 102 if (bar_nr == 3 && bar->bar2_halve) 103 bar_len >>= 1; 104 105 ret = nvkm_vm_new(device, 0, bar_len, 0, key, &vm); 106 if (ret) 107 return ret; 108 109 atomic_inc(&vm->engref[NVKM_SUBDEV_BAR]); 110 111 /* 112 * Bootstrap page table lookup. 113 */ 114 if (bar_nr == 3) { 115 ret = nvkm_vm_boot(vm, bar_len); 116 if (ret) { 117 nvkm_vm_ref(NULL, &vm, NULL); 118 return ret; 119 } 120 } 121 122 ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd); 123 nvkm_vm_ref(NULL, &vm, NULL); 124 if (ret) 125 return ret; 126 127 nvkm_kmap(bar_vm->mem); 128 nvkm_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); 129 nvkm_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); 130 nvkm_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); 131 nvkm_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); 132 nvkm_done(bar_vm->mem); 133 return 0; 134 } 135 136 int 137 gf100_bar_oneinit(struct nvkm_bar *base) 138 { 139 static struct lock_class_key bar1_lock; 140 static struct lock_class_key bar2_lock; 141 struct gf100_bar *bar = gf100_bar(base); 142 int ret; 143 144 /* BAR2 */ 145 if (bar->base.func->bar2.init) { 146 ret = gf100_bar_oneinit_bar(bar, &bar->bar[0], &bar2_lock, 3); 147 if (ret) 148 return ret; 149 150 bar->base.subdev.oneinit = true; 151 nvkm_bar_bar2_init(bar->base.subdev.device); 152 } 153 154 /* BAR1 */ 155 ret = gf100_bar_oneinit_bar(bar, &bar->bar[1], &bar1_lock, 1); 156 if (ret) 157 return ret; 158 159 return 0; 160 } 161 162 void * 163 gf100_bar_dtor(struct nvkm_bar *base) 164 { 165 struct gf100_bar *bar = gf100_bar(base); 166 167 nvkm_vm_ref(NULL, &bar->bar[1].vm, bar->bar[1].pgd); 168 nvkm_gpuobj_del(&bar->bar[1].pgd); 169 nvkm_memory_unref(&bar->bar[1].mem); 170 171 nvkm_vm_ref(NULL, &bar->bar[0].vm, bar->bar[0].pgd); 172 nvkm_gpuobj_del(&bar->bar[0].pgd); 173 nvkm_memory_unref(&bar->bar[0].mem); 174 return bar; 175 } 176 177 int 178 gf100_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device, 179 int index, struct nvkm_bar **pbar) 180 { 181 struct gf100_bar *bar; 182 if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL))) 183 return -ENOMEM; 184 nvkm_bar_ctor(func, device, index, &bar->base); 185 bar->bar2_halve = nvkm_boolopt(device->cfgopt, "NvBar2Halve", false); 186 *pbar = &bar->base; 187 return 0; 188 } 189 190 static const struct nvkm_bar_func 191 gf100_bar_func = { 192 .dtor = gf100_bar_dtor, 193 .oneinit = gf100_bar_oneinit, 194 .bar1.init = gf100_bar_bar1_init, 195 .bar1.fini = gf100_bar_bar1_fini, 196 .bar1.wait = gf100_bar_bar1_wait, 197 .bar1.vmm = gf100_bar_bar1_vmm, 198 .bar2.init = gf100_bar_bar2_init, 199 .bar2.fini = gf100_bar_bar2_fini, 200 .bar2.wait = gf100_bar_bar1_wait, 201 .bar2.vmm = gf100_bar_bar2_vmm, 202 .flush = g84_bar_flush, 203 }; 204 205 int 206 gf100_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) 207 { 208 return gf100_bar_new_(&gf100_bar_func, device, index, pbar); 209 } 210