1 /*
2  * Copyright 2019 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include "priv.h"
23 
24 #include <core/firmware.h>
25 #include <core/memory.h>
26 #include <subdev/gsp.h>
27 #include <subdev/pmu.h>
28 #include <engine/sec2.h>
29 
30 #include <nvfw/acr.h>
31 
32 static int
33 tu102_acr_init(struct nvkm_acr *acr)
34 {
35 	int ret = nvkm_acr_hsf_boot(acr, "AHESASC");
36 	if (ret)
37 		return ret;
38 
39 	return nvkm_acr_hsf_boot(acr, "ASB");
40 }
41 
42 static int
43 tu102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
44 {
45 	struct nvkm_acr_lsfw *lsfw;
46 	u32 offset = 0;
47 	int ret;
48 
49 	/*XXX: shared sub-WPR headers, fill terminator for now. */
50 	nvkm_wo32(acr->wpr, 0x200, 0xffffffff);
51 
52 	/* Fill per-LSF structures. */
53 	list_for_each_entry(lsfw, &acr->lsfw, head) {
54 		struct lsf_signature_v1 *sig = (void *)lsfw->sig->data;
55 		struct wpr_header_v1 hdr = {
56 			.falcon_id = lsfw->id,
57 			.lsb_offset = lsfw->offset.lsb,
58 			.bootstrap_owner = NVKM_ACR_LSF_GSPLITE,
59 			.lazy_bootstrap = 1,
60 			.bin_version = sig->version,
61 			.status = WPR_HEADER_V1_STATUS_COPY,
62 		};
63 
64 		/* Write WPR header. */
65 		nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
66 		offset += sizeof(hdr);
67 
68 		/* Write LSB header. */
69 		ret = gp102_acr_wpr_build_lsb(acr, lsfw);
70 		if (ret)
71 			return ret;
72 
73 		/* Write ucode image. */
74 		nvkm_wobj(acr->wpr, lsfw->offset.img,
75 				    lsfw->img.data,
76 				    lsfw->img.size);
77 
78 		/* Write bootloader data. */
79 		lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
80 	}
81 
82 	/* Finalise WPR. */
83 	nvkm_wo32(acr->wpr, offset, WPR_HEADER_V1_FALCON_ID_INVALID);
84 	return 0;
85 }
86 
87 static int
88 tu102_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
89 {
90 	return gm200_acr_hsfw_boot(acr, hsf, 0, 0);
91 }
92 
93 static int
94 tu102_acr_hsfw_nofw(struct nvkm_acr *acr, const char *bl, const char *fw,
95 		    const char *name, int version,
96 		    const struct nvkm_acr_hsf_fwif *fwif)
97 {
98 	return 0;
99 }
100 
101 MODULE_FIRMWARE("nvidia/tu102/acr/unload_bl.bin");
102 MODULE_FIRMWARE("nvidia/tu102/acr/ucode_unload.bin");
103 
104 MODULE_FIRMWARE("nvidia/tu104/acr/unload_bl.bin");
105 MODULE_FIRMWARE("nvidia/tu104/acr/ucode_unload.bin");
106 
107 MODULE_FIRMWARE("nvidia/tu106/acr/unload_bl.bin");
108 MODULE_FIRMWARE("nvidia/tu106/acr/ucode_unload.bin");
109 
110 MODULE_FIRMWARE("nvidia/tu116/acr/unload_bl.bin");
111 MODULE_FIRMWARE("nvidia/tu116/acr/ucode_unload.bin");
112 
113 MODULE_FIRMWARE("nvidia/tu117/acr/unload_bl.bin");
114 MODULE_FIRMWARE("nvidia/tu117/acr/ucode_unload.bin");
115 
116 static const struct nvkm_acr_hsf_fwif
117 tu102_acr_unload_fwif[] = {
118 	{  0, nvkm_acr_hsfw_load, &gp108_acr_unload_0 },
119 	{ -1, tu102_acr_hsfw_nofw },
120 	{}
121 };
122 
123 static int
124 tu102_acr_asb_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
125 {
126 	return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->gsp->falcon);
127 }
128 
129 static const struct nvkm_acr_hsf_func
130 tu102_acr_asb_0 = {
131 	.load = tu102_acr_asb_load,
132 	.boot = tu102_acr_hsfw_boot,
133 	.bld = gp108_acr_hsfw_bld,
134 };
135 
136 MODULE_FIRMWARE("nvidia/tu102/acr/ucode_asb.bin");
137 MODULE_FIRMWARE("nvidia/tu104/acr/ucode_asb.bin");
138 MODULE_FIRMWARE("nvidia/tu106/acr/ucode_asb.bin");
139 MODULE_FIRMWARE("nvidia/tu116/acr/ucode_asb.bin");
140 MODULE_FIRMWARE("nvidia/tu117/acr/ucode_asb.bin");
141 
142 static const struct nvkm_acr_hsf_fwif
143 tu102_acr_asb_fwif[] = {
144 	{  0, nvkm_acr_hsfw_load, &tu102_acr_asb_0 },
145 	{ -1, tu102_acr_hsfw_nofw },
146 	{}
147 };
148 
149 static const struct nvkm_acr_hsf_func
150 tu102_acr_ahesasc_0 = {
151 	.load = gp102_acr_load_load,
152 	.boot = tu102_acr_hsfw_boot,
153 	.bld = gp108_acr_hsfw_bld,
154 };
155 
156 MODULE_FIRMWARE("nvidia/tu102/acr/bl.bin");
157 MODULE_FIRMWARE("nvidia/tu102/acr/ucode_ahesasc.bin");
158 
159 MODULE_FIRMWARE("nvidia/tu104/acr/bl.bin");
160 MODULE_FIRMWARE("nvidia/tu104/acr/ucode_ahesasc.bin");
161 
162 MODULE_FIRMWARE("nvidia/tu106/acr/bl.bin");
163 MODULE_FIRMWARE("nvidia/tu106/acr/ucode_ahesasc.bin");
164 
165 MODULE_FIRMWARE("nvidia/tu116/acr/bl.bin");
166 MODULE_FIRMWARE("nvidia/tu116/acr/ucode_ahesasc.bin");
167 
168 MODULE_FIRMWARE("nvidia/tu117/acr/bl.bin");
169 MODULE_FIRMWARE("nvidia/tu117/acr/ucode_ahesasc.bin");
170 
171 static const struct nvkm_acr_hsf_fwif
172 tu102_acr_ahesasc_fwif[] = {
173 	{  0, nvkm_acr_hsfw_load, &tu102_acr_ahesasc_0 },
174 	{ -1, tu102_acr_hsfw_nofw },
175 	{}
176 };
177 
178 static const struct nvkm_acr_func
179 tu102_acr = {
180 	.ahesasc = tu102_acr_ahesasc_fwif,
181 	.asb = tu102_acr_asb_fwif,
182 	.unload = tu102_acr_unload_fwif,
183 	.wpr_parse = gp102_acr_wpr_parse,
184 	.wpr_layout = gp102_acr_wpr_layout,
185 	.wpr_alloc = gp102_acr_wpr_alloc,
186 	.wpr_patch = gp102_acr_wpr_patch,
187 	.wpr_build = tu102_acr_wpr_build,
188 	.wpr_check = gm200_acr_wpr_check,
189 	.init = tu102_acr_init,
190 };
191 
192 static int
193 tu102_acr_load(struct nvkm_acr *acr, int version,
194 	       const struct nvkm_acr_fwif *fwif)
195 {
196 	struct nvkm_subdev *subdev = &acr->subdev;
197 	const struct nvkm_acr_hsf_fwif *hsfwif;
198 
199 	hsfwif = nvkm_firmware_load(subdev, fwif->func->ahesasc, "AcrAHESASC",
200 				    acr, "acr/bl", "acr/ucode_ahesasc",
201 				    "AHESASC");
202 	if (IS_ERR(hsfwif))
203 		return PTR_ERR(hsfwif);
204 
205 	hsfwif = nvkm_firmware_load(subdev, fwif->func->asb, "AcrASB",
206 				    acr, "acr/bl", "acr/ucode_asb", "ASB");
207 	if (IS_ERR(hsfwif))
208 		return PTR_ERR(hsfwif);
209 
210 	hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
211 				    acr, "acr/unload_bl", "acr/ucode_unload",
212 				    "unload");
213 	if (IS_ERR(hsfwif))
214 		return PTR_ERR(hsfwif);
215 
216 	return 0;
217 }
218 
219 static const struct nvkm_acr_fwif
220 tu102_acr_fwif[] = {
221 	{  0, tu102_acr_load, &tu102_acr },
222 	{ -1, gm200_acr_nofw, &gm200_acr },
223 	{}
224 };
225 
226 int
227 tu102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
228 	      struct nvkm_acr **pacr)
229 {
230 	return nvkm_acr_new_(tu102_acr_fwif, device, type, inst, pacr);
231 }
232