1 /* 2 * Copyright 2019 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "priv.h" 23 24 #include <core/firmware.h> 25 #include <core/memory.h> 26 #include <subdev/mmu.h> 27 #include <engine/sec2.h> 28 29 #include <nvfw/acr.h> 30 #include <nvfw/flcn.h> 31 32 void 33 gp102_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust) 34 { 35 struct wpr_header_v1 hdr; 36 struct lsb_header_v1 lsb; 37 struct nvkm_acr_lsfw *lsfw; 38 u32 offset = 0; 39 40 do { 41 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr)); 42 wpr_header_v1_dump(&acr->subdev, &hdr); 43 44 list_for_each_entry(lsfw, &acr->lsfw, head) { 45 if (lsfw->id != hdr.falcon_id) 46 continue; 47 48 nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb)); 49 lsb_header_v1_dump(&acr->subdev, &lsb); 50 51 lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust); 52 break; 53 } 54 55 offset += sizeof(hdr); 56 } while (hdr.falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID); 57 } 58 59 int 60 gp102_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw) 61 { 62 struct lsb_header_v1 hdr; 63 64 if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature))) 65 return -EINVAL; 66 67 memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size); 68 gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail); 69 70 nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr)); 71 return 0; 72 } 73 74 int 75 gp102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) 76 { 77 struct nvkm_acr_lsfw *lsfw; 78 u32 offset = 0; 79 int ret; 80 81 /* Fill per-LSF structures. */ 82 list_for_each_entry(lsfw, &acr->lsfw, head) { 83 struct lsf_signature_v1 *sig = (void *)lsfw->sig->data; 84 struct wpr_header_v1 hdr = { 85 .falcon_id = lsfw->id, 86 .lsb_offset = lsfw->offset.lsb, 87 .bootstrap_owner = NVKM_ACR_LSF_SEC2, 88 .lazy_bootstrap = rtos && lsfw->id != rtos->id, 89 .bin_version = sig->version, 90 .status = WPR_HEADER_V1_STATUS_COPY, 91 }; 92 93 /* Write WPR header. */ 94 nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr)); 95 offset += sizeof(hdr); 96 97 /* Write LSB header. */ 98 ret = gp102_acr_wpr_build_lsb(acr, lsfw); 99 if (ret) 100 return ret; 101 102 /* Write ucode image. */ 103 nvkm_wobj(acr->wpr, lsfw->offset.img, 104 lsfw->img.data, 105 lsfw->img.size); 106 107 /* Write bootloader data. */ 108 lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw); 109 } 110 111 /* Finalise WPR. */ 112 nvkm_wo32(acr->wpr, offset, WPR_HEADER_V1_FALCON_ID_INVALID); 113 return 0; 114 } 115 116 int 117 gp102_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size) 118 { 119 int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST, 120 ALIGN(wpr_size, 0x40000) << 1, 0x40000, true, 121 &acr->wpr); 122 if (ret) 123 return ret; 124 125 acr->shadow_start = nvkm_memory_addr(acr->wpr); 126 acr->wpr_start = acr->shadow_start + (nvkm_memory_size(acr->wpr) >> 1); 127 acr->wpr_end = acr->wpr_start + (nvkm_memory_size(acr->wpr) >> 1); 128 return 0; 129 } 130 131 u32 132 gp102_acr_wpr_layout(struct nvkm_acr *acr) 133 { 134 struct nvkm_acr_lsfw *lsfw; 135 u32 wpr = 0; 136 137 wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header_v1); 138 wpr = ALIGN(wpr, 256); 139 140 wpr += 0x100; /* Shared sub-WPR headers. */ 141 142 list_for_each_entry(lsfw, &acr->lsfw, head) { 143 wpr = ALIGN(wpr, 256); 144 lsfw->offset.lsb = wpr; 145 wpr += sizeof(struct lsb_header_v1); 146 147 wpr = ALIGN(wpr, 4096); 148 lsfw->offset.img = wpr; 149 wpr += lsfw->img.size; 150 151 wpr = ALIGN(wpr, 256); 152 lsfw->offset.bld = wpr; 153 lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256); 154 wpr += lsfw->bl_data_size; 155 } 156 157 return wpr; 158 } 159 160 int 161 gp102_acr_wpr_parse(struct nvkm_acr *acr) 162 { 163 const struct wpr_header_v1 *hdr = (void *)acr->wpr_fw->data; 164 165 while (hdr->falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID) { 166 wpr_header_v1_dump(&acr->subdev, hdr); 167 if (!nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id)) 168 return -ENOMEM; 169 } 170 171 return 0; 172 } 173 174 MODULE_FIRMWARE("nvidia/gp102/acr/unload_bl.bin"); 175 MODULE_FIRMWARE("nvidia/gp102/acr/ucode_unload.bin"); 176 177 MODULE_FIRMWARE("nvidia/gp104/acr/unload_bl.bin"); 178 MODULE_FIRMWARE("nvidia/gp104/acr/ucode_unload.bin"); 179 180 MODULE_FIRMWARE("nvidia/gp106/acr/unload_bl.bin"); 181 MODULE_FIRMWARE("nvidia/gp106/acr/ucode_unload.bin"); 182 183 MODULE_FIRMWARE("nvidia/gp107/acr/unload_bl.bin"); 184 MODULE_FIRMWARE("nvidia/gp107/acr/ucode_unload.bin"); 185 186 static const struct nvkm_acr_hsf_fwif 187 gp102_acr_unload_fwif[] = { 188 { 0, nvkm_acr_hsfw_load, &gm200_acr_unload_0 }, 189 {} 190 }; 191 192 int 193 gp102_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw) 194 { 195 struct flcn_acr_desc_v1 *desc = (void *)&hsfw->image[hsfw->data_addr]; 196 197 desc->wpr_region_id = 1; 198 desc->regions.no_regions = 2; 199 desc->regions.region_props[0].start_addr = acr->wpr_start >> 8; 200 desc->regions.region_props[0].end_addr = acr->wpr_end >> 8; 201 desc->regions.region_props[0].region_id = 1; 202 desc->regions.region_props[0].read_mask = 0xf; 203 desc->regions.region_props[0].write_mask = 0xc; 204 desc->regions.region_props[0].client_mask = 0x2; 205 desc->regions.region_props[0].shadow_mem_start_addr = 206 acr->shadow_start >> 8; 207 flcn_acr_desc_v1_dump(&acr->subdev, desc); 208 209 return gm200_acr_hsfw_load(acr, hsfw, 210 &acr->subdev.device->sec2->falcon); 211 } 212 213 static const struct nvkm_acr_hsf_func 214 gp102_acr_load_0 = { 215 .load = gp102_acr_load_load, 216 .boot = gm200_acr_load_boot, 217 .bld = gm200_acr_hsfw_bld, 218 }; 219 220 MODULE_FIRMWARE("nvidia/gp102/acr/bl.bin"); 221 MODULE_FIRMWARE("nvidia/gp102/acr/ucode_load.bin"); 222 223 MODULE_FIRMWARE("nvidia/gp104/acr/bl.bin"); 224 MODULE_FIRMWARE("nvidia/gp104/acr/ucode_load.bin"); 225 226 MODULE_FIRMWARE("nvidia/gp106/acr/bl.bin"); 227 MODULE_FIRMWARE("nvidia/gp106/acr/ucode_load.bin"); 228 229 MODULE_FIRMWARE("nvidia/gp107/acr/bl.bin"); 230 MODULE_FIRMWARE("nvidia/gp107/acr/ucode_load.bin"); 231 232 static const struct nvkm_acr_hsf_fwif 233 gp102_acr_load_fwif[] = { 234 { 0, nvkm_acr_hsfw_load, &gp102_acr_load_0 }, 235 {} 236 }; 237 238 static const struct nvkm_acr_func 239 gp102_acr = { 240 .load = gp102_acr_load_fwif, 241 .unload = gp102_acr_unload_fwif, 242 .wpr_parse = gp102_acr_wpr_parse, 243 .wpr_layout = gp102_acr_wpr_layout, 244 .wpr_alloc = gp102_acr_wpr_alloc, 245 .wpr_build = gp102_acr_wpr_build, 246 .wpr_patch = gp102_acr_wpr_patch, 247 .wpr_check = gm200_acr_wpr_check, 248 .init = gm200_acr_init, 249 }; 250 251 int 252 gp102_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) 253 { 254 struct nvkm_subdev *subdev = &acr->subdev; 255 const struct nvkm_acr_hsf_fwif *hsfwif; 256 257 hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad", 258 acr, "acr/bl", "acr/ucode_load", "load"); 259 if (IS_ERR(hsfwif)) 260 return PTR_ERR(hsfwif); 261 262 hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload", 263 acr, "acr/unload_bl", "acr/ucode_unload", 264 "unload"); 265 if (IS_ERR(hsfwif)) 266 return PTR_ERR(hsfwif); 267 268 return 0; 269 } 270 271 static const struct nvkm_acr_fwif 272 gp102_acr_fwif[] = { 273 { 0, gp102_acr_load, &gp102_acr }, 274 { -1, gm200_acr_nofw, &gm200_acr }, 275 {} 276 }; 277 278 int 279 gp102_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr) 280 { 281 return nvkm_acr_new_(gp102_acr_fwif, device, index, pacr); 282 } 283