1 /* 2 * Copyright 2013 Ilia Mirkin 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include <engine/xtensa.h> 23 24 #include <core/engctx.h> 25 26 u32 27 _nvkm_xtensa_rd32(struct nvkm_object *object, u64 addr) 28 { 29 struct nvkm_xtensa *xtensa = (void *)object; 30 return nv_rd32(xtensa, xtensa->addr + addr); 31 } 32 33 void 34 _nvkm_xtensa_wr32(struct nvkm_object *object, u64 addr, u32 data) 35 { 36 struct nvkm_xtensa *xtensa = (void *)object; 37 nv_wr32(xtensa, xtensa->addr + addr, data); 38 } 39 40 int 41 _nvkm_xtensa_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 42 struct nvkm_oclass *oclass, void *data, u32 size, 43 struct nvkm_object **pobject) 44 { 45 struct nvkm_engctx *engctx; 46 int ret; 47 48 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, 0x1000, 49 NVOBJ_FLAG_ZERO_ALLOC, &engctx); 50 *pobject = nv_object(engctx); 51 return ret; 52 } 53 54 void 55 _nvkm_xtensa_intr(struct nvkm_subdev *subdev) 56 { 57 struct nvkm_xtensa *xtensa = (void *)subdev; 58 u32 unk104 = nv_ro32(xtensa, 0xd04); 59 u32 intr = nv_ro32(xtensa, 0xc20); 60 u32 chan = nv_ro32(xtensa, 0xc28); 61 u32 unk10c = nv_ro32(xtensa, 0xd0c); 62 63 if (intr & 0x10) 64 nv_warn(xtensa, "Watchdog interrupt, engine hung.\n"); 65 nv_wo32(xtensa, 0xc20, intr); 66 intr = nv_ro32(xtensa, 0xc20); 67 if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { 68 nv_debug(xtensa, "Enabling FIFO_CTRL\n"); 69 nv_mask(xtensa, xtensa->addr + 0xd94, 0, xtensa->fifo_val); 70 } 71 } 72 73 int 74 nvkm_xtensa_create_(struct nvkm_object *parent, struct nvkm_object *engine, 75 struct nvkm_oclass *oclass, u32 addr, bool enable, 76 const char *iname, const char *fname, 77 int length, void **pobject) 78 { 79 struct nvkm_xtensa *xtensa; 80 int ret; 81 82 ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, 83 fname, length, pobject); 84 xtensa = *pobject; 85 if (ret) 86 return ret; 87 88 nv_subdev(xtensa)->intr = _nvkm_xtensa_intr; 89 xtensa->addr = addr; 90 return 0; 91 } 92 93 int 94 _nvkm_xtensa_init(struct nvkm_object *object) 95 { 96 struct nvkm_device *device = nv_device(object); 97 struct nvkm_xtensa *xtensa = (void *)object; 98 const struct firmware *fw; 99 char name[32]; 100 int i, ret; 101 u32 tmp; 102 103 ret = nvkm_engine_init(&xtensa->engine); 104 if (ret) 105 return ret; 106 107 if (!xtensa->gpu_fw) { 108 snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x", 109 xtensa->addr >> 12); 110 111 ret = request_firmware(&fw, name, nv_device_base(device)); 112 if (ret) { 113 nv_warn(xtensa, "unable to load firmware %s\n", name); 114 return ret; 115 } 116 117 if (fw->size > 0x40000) { 118 nv_warn(xtensa, "firmware %s too large\n", name); 119 release_firmware(fw); 120 return -EINVAL; 121 } 122 123 ret = nvkm_gpuobj_new(object, NULL, 0x40000, 0x1000, 0, 124 &xtensa->gpu_fw); 125 if (ret) { 126 release_firmware(fw); 127 return ret; 128 } 129 130 nv_debug(xtensa, "Loading firmware to address: 0x%llx\n", 131 xtensa->gpu_fw->addr); 132 133 for (i = 0; i < fw->size / 4; i++) 134 nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i)); 135 release_firmware(fw); 136 } 137 138 nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */ 139 nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */ 140 141 nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */ 142 nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ 143 nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ 144 145 nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */ 146 nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */ 147 nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */ 148 149 tmp = nv_rd32(xtensa, 0x0); 150 nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */ 151 152 nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */ 153 154 nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ 155 nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ 156 return 0; 157 } 158 159 int 160 _nvkm_xtensa_fini(struct nvkm_object *object, bool suspend) 161 { 162 struct nvkm_xtensa *xtensa = (void *)object; 163 164 nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */ 165 nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */ 166 167 if (!suspend) 168 nvkm_gpuobj_ref(NULL, &xtensa->gpu_fw); 169 170 return nvkm_engine_fini(&xtensa->engine, suspend); 171 } 172