1 /* 2 * Copyright 2013 Ilia Mirkin 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include <engine/xtensa.h> 23 24 #include <core/engctx.h> 25 26 u32 27 _nvkm_xtensa_rd32(struct nvkm_object *object, u64 addr) 28 { 29 struct nvkm_xtensa *xtensa = (void *)object; 30 return nvkm_rd32(xtensa->engine.subdev.device, xtensa->addr + addr); 31 } 32 33 void 34 _nvkm_xtensa_wr32(struct nvkm_object *object, u64 addr, u32 data) 35 { 36 struct nvkm_xtensa *xtensa = (void *)object; 37 nvkm_wr32(xtensa->engine.subdev.device, xtensa->addr + addr, data); 38 } 39 40 int 41 _nvkm_xtensa_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 42 struct nvkm_oclass *oclass, void *data, u32 size, 43 struct nvkm_object **pobject) 44 { 45 struct nvkm_engctx *engctx; 46 int ret; 47 48 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, 0x1000, 49 NVOBJ_FLAG_ZERO_ALLOC, &engctx); 50 *pobject = nv_object(engctx); 51 return ret; 52 } 53 54 void 55 _nvkm_xtensa_intr(struct nvkm_subdev *subdev) 56 { 57 struct nvkm_xtensa *xtensa = (void *)subdev; 58 struct nvkm_device *device = xtensa->engine.subdev.device; 59 u32 unk104 = nv_ro32(xtensa, 0xd04); 60 u32 intr = nv_ro32(xtensa, 0xc20); 61 u32 chan = nv_ro32(xtensa, 0xc28); 62 u32 unk10c = nv_ro32(xtensa, 0xd0c); 63 64 if (intr & 0x10) 65 nvkm_warn(subdev, "Watchdog interrupt, engine hung.\n"); 66 nv_wo32(xtensa, 0xc20, intr); 67 intr = nv_ro32(xtensa, 0xc20); 68 if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { 69 nvkm_debug(subdev, "Enabling FIFO_CTRL\n"); 70 nvkm_mask(device, xtensa->addr + 0xd94, 0, xtensa->fifo_val); 71 } 72 } 73 74 int 75 nvkm_xtensa_create_(struct nvkm_object *parent, struct nvkm_object *engine, 76 struct nvkm_oclass *oclass, u32 addr, bool enable, 77 const char *iname, const char *fname, 78 int length, void **pobject) 79 { 80 struct nvkm_xtensa *xtensa; 81 int ret; 82 83 ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, 84 fname, length, pobject); 85 xtensa = *pobject; 86 if (ret) 87 return ret; 88 89 nv_subdev(xtensa)->intr = _nvkm_xtensa_intr; 90 xtensa->addr = addr; 91 return 0; 92 } 93 94 int 95 _nvkm_xtensa_init(struct nvkm_object *object) 96 { 97 struct nvkm_xtensa *xtensa = (void *)object; 98 struct nvkm_subdev *subdev = &xtensa->engine.subdev; 99 struct nvkm_device *device = subdev->device; 100 const struct firmware *fw; 101 char name[32]; 102 int i, ret; 103 u32 tmp; 104 105 ret = nvkm_engine_init(&xtensa->engine); 106 if (ret) 107 return ret; 108 109 if (!xtensa->gpu_fw) { 110 snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x", 111 xtensa->addr >> 12); 112 113 ret = request_firmware(&fw, name, nv_device_base(device)); 114 if (ret) { 115 nvkm_warn(subdev, "unable to load firmware %s\n", name); 116 return ret; 117 } 118 119 if (fw->size > 0x40000) { 120 nvkm_warn(subdev, "firmware %s too large\n", name); 121 release_firmware(fw); 122 return -EINVAL; 123 } 124 125 ret = nvkm_gpuobj_new(object, NULL, 0x40000, 0x1000, 0, 126 &xtensa->gpu_fw); 127 if (ret) { 128 release_firmware(fw); 129 return ret; 130 } 131 132 nvkm_debug(subdev, "Loading firmware to address: %010llx\n", 133 xtensa->gpu_fw->addr); 134 135 for (i = 0; i < fw->size / 4; i++) 136 nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i)); 137 release_firmware(fw); 138 } 139 140 nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */ 141 nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */ 142 143 nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */ 144 nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ 145 nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ 146 147 nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */ 148 nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */ 149 nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */ 150 151 tmp = nvkm_rd32(device, 0x0); 152 nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */ 153 154 nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */ 155 156 nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ 157 nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ 158 return 0; 159 } 160 161 int 162 _nvkm_xtensa_fini(struct nvkm_object *object, bool suspend) 163 { 164 struct nvkm_xtensa *xtensa = (void *)object; 165 166 nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */ 167 nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */ 168 169 if (!suspend) 170 nvkm_gpuobj_ref(NULL, &xtensa->gpu_fw); 171 172 return nvkm_engine_fini(&xtensa->engine, suspend); 173 } 174