1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 26 #include <core/handle.h> 27 #include <core/namedb.h> 28 #include <engine/disp.h> 29 #include <subdev/bar.h> 30 31 #include <nvif/event.h> 32 33 /******************************************************************************* 34 * software object classes 35 ******************************************************************************/ 36 37 static int 38 nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd, 39 void *args, u32 size) 40 { 41 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); 42 struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)->parent; 43 struct nvkm_handle *handle; 44 int ret = -EINVAL; 45 46 handle = nvkm_namedb_get(nv_namedb(fifo), *(u32 *)args); 47 if (!handle) 48 return -ENOENT; 49 50 if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { 51 struct nvkm_gpuobj *gpuobj = nv_gpuobj(handle->object); 52 chan->vblank.ctxdma = gpuobj->node->offset >> 4; 53 ret = 0; 54 } 55 nvkm_namedb_put(handle); 56 return ret; 57 } 58 59 static int 60 nv50_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd, 61 void *args, u32 size) 62 { 63 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); 64 chan->vblank.offset = *(u32 *)args; 65 return 0; 66 } 67 68 int 69 nv50_sw_mthd_vblsem_value(struct nvkm_object *object, u32 mthd, 70 void *args, u32 size) 71 { 72 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); 73 chan->vblank.value = *(u32 *)args; 74 return 0; 75 } 76 77 int 78 nv50_sw_mthd_vblsem_release(struct nvkm_object *object, u32 mthd, 79 void *args, u32 size) 80 { 81 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); 82 u32 head = *(u32 *)args; 83 if (head >= nvkm_disp(chan)->vblank.index_nr) 84 return -EINVAL; 85 86 nvkm_notify_get(&chan->vblank.notify[head]); 87 return 0; 88 } 89 90 int 91 nv50_sw_mthd_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size) 92 { 93 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); 94 if (chan->base.flip) 95 return chan->base.flip(chan->base.flip_data); 96 return -EINVAL; 97 } 98 99 static struct nvkm_omthds 100 nv50_sw_omthds[] = { 101 { 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem }, 102 { 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset }, 103 { 0x0404, 0x0404, nv50_sw_mthd_vblsem_value }, 104 { 0x0408, 0x0408, nv50_sw_mthd_vblsem_release }, 105 { 0x0500, 0x0500, nv50_sw_mthd_flip }, 106 {} 107 }; 108 109 static struct nvkm_oclass 110 nv50_sw_sclass[] = { 111 { 0x506e, &nvkm_object_ofuncs, nv50_sw_omthds }, 112 {} 113 }; 114 115 /******************************************************************************* 116 * software context 117 ******************************************************************************/ 118 119 static int 120 nv50_sw_vblsem_release(struct nvkm_notify *notify) 121 { 122 struct nv50_sw_chan *chan = 123 container_of(notify, typeof(*chan), vblank.notify[notify->index]); 124 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; 125 struct nvkm_bar *bar = nvkm_bar(priv); 126 127 nv_wr32(priv, 0x001704, chan->vblank.channel); 128 nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); 129 bar->flush(bar); 130 131 if (nv_device(priv)->chipset == 0x50) { 132 nv_wr32(priv, 0x001570, chan->vblank.offset); 133 nv_wr32(priv, 0x001574, chan->vblank.value); 134 } else { 135 nv_wr32(priv, 0x060010, chan->vblank.offset); 136 nv_wr32(priv, 0x060014, chan->vblank.value); 137 } 138 139 return NVKM_NOTIFY_DROP; 140 } 141 142 void 143 nv50_sw_context_dtor(struct nvkm_object *object) 144 { 145 struct nv50_sw_chan *chan = (void *)object; 146 int i; 147 148 for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++) 149 nvkm_notify_fini(&chan->vblank.notify[i]); 150 151 nvkm_sw_context_destroy(&chan->base); 152 } 153 154 int 155 nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 156 struct nvkm_oclass *oclass, void *data, u32 size, 157 struct nvkm_object **pobject) 158 { 159 struct nvkm_disp *disp = nvkm_disp(parent); 160 struct nv50_sw_cclass *pclass = (void *)oclass; 161 struct nv50_sw_chan *chan; 162 int ret, i; 163 164 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); 165 *pobject = nv_object(chan); 166 if (ret) 167 return ret; 168 169 for (i = 0; disp && i < disp->vblank.index_nr; i++) { 170 ret = nvkm_notify_init(NULL, &disp->vblank, pclass->vblank, 171 false, 172 &(struct nvif_notify_head_req_v0) { 173 .head = i, 174 }, 175 sizeof(struct nvif_notify_head_req_v0), 176 sizeof(struct nvif_notify_head_rep_v0), 177 &chan->vblank.notify[i]); 178 if (ret) 179 return ret; 180 } 181 182 chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12; 183 return 0; 184 } 185 186 static struct nv50_sw_cclass 187 nv50_sw_cclass = { 188 .base.handle = NV_ENGCTX(SW, 0x50), 189 .base.ofuncs = &(struct nvkm_ofuncs) { 190 .ctor = nv50_sw_context_ctor, 191 .dtor = nv50_sw_context_dtor, 192 .init = _nvkm_sw_context_init, 193 .fini = _nvkm_sw_context_fini, 194 }, 195 .vblank = nv50_sw_vblsem_release, 196 }; 197 198 /******************************************************************************* 199 * software engine/subdev functions 200 ******************************************************************************/ 201 202 int 203 nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 204 struct nvkm_oclass *oclass, void *data, u32 size, 205 struct nvkm_object **pobject) 206 { 207 struct nv50_sw_oclass *pclass = (void *)oclass; 208 struct nv50_sw_priv *priv; 209 int ret; 210 211 ret = nvkm_sw_create(parent, engine, oclass, &priv); 212 *pobject = nv_object(priv); 213 if (ret) 214 return ret; 215 216 nv_engine(priv)->cclass = pclass->cclass; 217 nv_engine(priv)->sclass = pclass->sclass; 218 nv_subdev(priv)->intr = nv04_sw_intr; 219 return 0; 220 } 221 222 struct nvkm_oclass * 223 nv50_sw_oclass = &(struct nv50_sw_oclass) { 224 .base.handle = NV_ENGINE(SW, 0x50), 225 .base.ofuncs = &(struct nvkm_ofuncs) { 226 .ctor = nv50_sw_ctor, 227 .dtor = _nvkm_sw_dtor, 228 .init = _nvkm_sw_init, 229 .fini = _nvkm_sw_fini, 230 }, 231 .cclass = &nv50_sw_cclass.base, 232 .sclass = nv50_sw_sclass, 233 }.base; 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