1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 26 #include <core/handle.h> 27 #include <core/namedb.h> 28 #include <engine/disp.h> 29 #include <subdev/bar.h> 30 31 #include <nvif/event.h> 32 #include <nvif/ioctl.h> 33 34 /******************************************************************************* 35 * software object classes 36 ******************************************************************************/ 37 38 static int 39 nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd, 40 void *args, u32 size) 41 { 42 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); 43 struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)->parent; 44 struct nvkm_handle *handle; 45 int ret = -EINVAL; 46 47 handle = nvkm_namedb_get(nv_namedb(fifo), *(u32 *)args); 48 if (!handle) 49 return -ENOENT; 50 51 if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { 52 struct nvkm_gpuobj *gpuobj = nv_gpuobj(handle->object); 53 chan->vblank.ctxdma = gpuobj->node->offset >> 4; 54 ret = 0; 55 } 56 nvkm_namedb_put(handle); 57 return ret; 58 } 59 60 static int 61 nv50_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd, 62 void *args, u32 size) 63 { 64 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); 65 chan->vblank.offset = *(u32 *)args; 66 return 0; 67 } 68 69 int 70 nv50_sw_mthd_vblsem_value(struct nvkm_object *object, u32 mthd, 71 void *args, u32 size) 72 { 73 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); 74 chan->vblank.value = *(u32 *)args; 75 return 0; 76 } 77 78 int 79 nv50_sw_mthd_vblsem_release(struct nvkm_object *object, u32 mthd, 80 void *args, u32 size) 81 { 82 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); 83 u32 head = *(u32 *)args; 84 if (head >= nvkm_disp(chan)->vblank.index_nr) 85 return -EINVAL; 86 87 nvkm_notify_get(&chan->vblank.notify[head]); 88 return 0; 89 } 90 91 int 92 nv50_sw_mthd_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size) 93 { 94 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent); 95 if (chan->base.flip) 96 return chan->base.flip(chan->base.flip_data); 97 return -EINVAL; 98 } 99 100 static struct nvkm_omthds 101 nv50_sw_omthds[] = { 102 { 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem }, 103 { 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset }, 104 { 0x0404, 0x0404, nv50_sw_mthd_vblsem_value }, 105 { 0x0408, 0x0408, nv50_sw_mthd_vblsem_release }, 106 { 0x0500, 0x0500, nv50_sw_mthd_flip }, 107 {} 108 }; 109 110 static struct nvkm_oclass 111 nv50_sw_sclass[] = { 112 { NVIF_IOCTL_NEW_V0_SW_NV50, &nvkm_object_ofuncs, nv50_sw_omthds }, 113 {} 114 }; 115 116 /******************************************************************************* 117 * software context 118 ******************************************************************************/ 119 120 static int 121 nv50_sw_vblsem_release(struct nvkm_notify *notify) 122 { 123 struct nv50_sw_chan *chan = 124 container_of(notify, typeof(*chan), vblank.notify[notify->index]); 125 struct nvkm_sw *sw = (void *)nv_object(chan)->engine; 126 struct nvkm_device *device = sw->engine.subdev.device; 127 struct nvkm_bar *bar = device->bar; 128 129 nvkm_wr32(device, 0x001704, chan->vblank.channel); 130 nvkm_wr32(device, 0x001710, 0x80000000 | chan->vblank.ctxdma); 131 bar->flush(bar); 132 133 if (nv_device(sw)->chipset == 0x50) { 134 nvkm_wr32(device, 0x001570, chan->vblank.offset); 135 nvkm_wr32(device, 0x001574, chan->vblank.value); 136 } else { 137 nvkm_wr32(device, 0x060010, chan->vblank.offset); 138 nvkm_wr32(device, 0x060014, chan->vblank.value); 139 } 140 141 return NVKM_NOTIFY_DROP; 142 } 143 144 void 145 nv50_sw_context_dtor(struct nvkm_object *object) 146 { 147 struct nv50_sw_chan *chan = (void *)object; 148 int i; 149 150 for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++) 151 nvkm_notify_fini(&chan->vblank.notify[i]); 152 153 nvkm_sw_context_destroy(&chan->base); 154 } 155 156 int 157 nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 158 struct nvkm_oclass *oclass, void *data, u32 size, 159 struct nvkm_object **pobject) 160 { 161 struct nvkm_disp *disp = nvkm_disp(parent); 162 struct nv50_sw_cclass *pclass = (void *)oclass; 163 struct nv50_sw_chan *chan; 164 int ret, i; 165 166 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); 167 *pobject = nv_object(chan); 168 if (ret) 169 return ret; 170 171 for (i = 0; disp && i < disp->vblank.index_nr; i++) { 172 ret = nvkm_notify_init(NULL, &disp->vblank, pclass->vblank, 173 false, 174 &(struct nvif_notify_head_req_v0) { 175 .head = i, 176 }, 177 sizeof(struct nvif_notify_head_req_v0), 178 sizeof(struct nvif_notify_head_rep_v0), 179 &chan->vblank.notify[i]); 180 if (ret) 181 return ret; 182 } 183 184 chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12; 185 return 0; 186 } 187 188 static struct nv50_sw_cclass 189 nv50_sw_cclass = { 190 .base.handle = NV_ENGCTX(SW, 0x50), 191 .base.ofuncs = &(struct nvkm_ofuncs) { 192 .ctor = nv50_sw_context_ctor, 193 .dtor = nv50_sw_context_dtor, 194 .init = _nvkm_sw_context_init, 195 .fini = _nvkm_sw_context_fini, 196 }, 197 .vblank = nv50_sw_vblsem_release, 198 }; 199 200 /******************************************************************************* 201 * software engine/subdev functions 202 ******************************************************************************/ 203 204 int 205 nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 206 struct nvkm_oclass *oclass, void *data, u32 size, 207 struct nvkm_object **pobject) 208 { 209 struct nv50_sw_oclass *pclass = (void *)oclass; 210 struct nvkm_sw *sw; 211 int ret; 212 213 ret = nvkm_sw_create(parent, engine, oclass, &sw); 214 *pobject = nv_object(sw); 215 if (ret) 216 return ret; 217 218 nv_engine(sw)->cclass = pclass->cclass; 219 nv_engine(sw)->sclass = pclass->sclass; 220 nv_subdev(sw)->intr = nv04_sw_intr; 221 return 0; 222 } 223 224 struct nvkm_oclass * 225 nv50_sw_oclass = &(struct nv50_sw_oclass) { 226 .base.handle = NV_ENGINE(SW, 0x50), 227 .base.ofuncs = &(struct nvkm_ofuncs) { 228 .ctor = nv50_sw_ctor, 229 .dtor = _nvkm_sw_dtor, 230 .init = _nvkm_sw_init, 231 .fini = _nvkm_sw_fini, 232 }, 233 .cclass = &nv50_sw_cclass.base, 234 .sclass = nv50_sw_sclass, 235 }.base; 236