1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv40.h" 25 26 static void 27 nv40_perfctr_init(struct nvkm_pm *pm, struct nvkm_perfdom *dom, 28 struct nvkm_perfctr *ctr) 29 { 30 struct nv40_pm_cntr *cntr = (void *)ctr; 31 u32 log = ctr->logic_op; 32 u32 src = 0x00000000; 33 int i; 34 35 for (i = 0; i < 4; i++) 36 src |= ctr->signal[i] << (i * 8); 37 38 nv_wr32(pm, 0x00a7c0 + dom->addr, 0x00000001 | (dom->mode << 4)); 39 nv_wr32(pm, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src); 40 nv_wr32(pm, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log); 41 } 42 43 static void 44 nv40_perfctr_read(struct nvkm_pm *pm, struct nvkm_perfdom *dom, 45 struct nvkm_perfctr *ctr) 46 { 47 struct nv40_pm_cntr *cntr = (void *)ctr; 48 49 switch (cntr->base.slot) { 50 case 0: cntr->base.ctr = nv_rd32(pm, 0x00a700 + dom->addr); break; 51 case 1: cntr->base.ctr = nv_rd32(pm, 0x00a6c0 + dom->addr); break; 52 case 2: cntr->base.ctr = nv_rd32(pm, 0x00a680 + dom->addr); break; 53 case 3: cntr->base.ctr = nv_rd32(pm, 0x00a740 + dom->addr); break; 54 } 55 dom->clk = nv_rd32(pm, 0x00a600 + dom->addr); 56 } 57 58 static void 59 nv40_perfctr_next(struct nvkm_pm *pm, struct nvkm_perfdom *dom) 60 { 61 if (pm->sequence != pm->sequence) { 62 nv_wr32(pm, 0x400084, 0x00000020); 63 pm->sequence = pm->sequence; 64 } 65 } 66 67 const struct nvkm_funcdom 68 nv40_perfctr_func = { 69 .init = nv40_perfctr_init, 70 .read = nv40_perfctr_read, 71 .next = nv40_perfctr_next, 72 }; 73 74 static const struct nvkm_specdom 75 nv40_pm[] = { 76 { 0x20, (const struct nvkm_specsig[]) { 77 {} 78 }, &nv40_perfctr_func }, 79 { 0x20, (const struct nvkm_specsig[]) { 80 {} 81 }, &nv40_perfctr_func }, 82 { 0x20, (const struct nvkm_specsig[]) { 83 {} 84 }, &nv40_perfctr_func }, 85 { 0x20, (const struct nvkm_specsig[]) { 86 {} 87 }, &nv40_perfctr_func }, 88 { 0x20, (const struct nvkm_specsig[]) { 89 {} 90 }, &nv40_perfctr_func }, 91 {} 92 }; 93 94 int 95 nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 96 struct nvkm_oclass *oclass, void *data, u32 size, 97 struct nvkm_object **pobject) 98 { 99 struct nv40_pm_oclass *mclass = (void *)oclass; 100 struct nv40_pm *pm; 101 int ret; 102 103 ret = nvkm_pm_create(parent, engine, oclass, &pm); 104 *pobject = nv_object(pm); 105 if (ret) 106 return ret; 107 108 ret = nvkm_perfdom_new(&pm->base, "pc", 0, 0, 0, 4, mclass->doms); 109 if (ret) 110 return ret; 111 112 nv_engine(pm)->cclass = &nvkm_pm_cclass; 113 nv_engine(pm)->sclass = nvkm_pm_sclass; 114 return 0; 115 } 116 117 struct nvkm_oclass * 118 nv40_pm_oclass = &(struct nv40_pm_oclass) { 119 .base.handle = NV_ENGINE(PM, 0x40), 120 .base.ofuncs = &(struct nvkm_ofuncs) { 121 .ctor = nv40_pm_ctor, 122 .dtor = _nvkm_pm_dtor, 123 .init = _nvkm_pm_init, 124 .fini = _nvkm_pm_fini, 125 }, 126 .doms = nv40_pm, 127 }.base; 128