1 /* 2 * Copyright 2015 Nouveau project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Samuel Pitoiset 23 */ 24 #include "nv40.h" 25 26 const struct nvkm_specsrc 27 gt200_crop_sources[] = { 28 { 0x407008, (const struct nvkm_specmux[]) { 29 { 0xf, 0, "sel0", true }, 30 { 0x1f, 16, "sel1", true }, 31 {} 32 }, "pgraph_rop0_crop_pm_mux" }, 33 {} 34 }; 35 36 const struct nvkm_specsrc 37 gt200_prop_sources[] = { 38 { 0x408750, (const struct nvkm_specmux[]) { 39 { 0x3f, 0, "sel", true }, 40 {} 41 }, "pgraph_tpc0_prop_pm_mux" }, 42 {} 43 }; 44 45 const struct nvkm_specsrc 46 gt200_tex_sources[] = { 47 { 0x408508, (const struct nvkm_specmux[]) { 48 { 0xfffff, 0, "unk0" }, 49 {} 50 }, "pgraph_tpc0_tex_unk08" }, 51 {} 52 }; 53 54 static const struct nvkm_specdom 55 gt200_pm[] = { 56 { 0x20, (const struct nvkm_specsig[]) { 57 {} 58 }, &nv40_perfctr_func }, 59 { 0xf0, (const struct nvkm_specsig[]) { 60 { 0xc9, "pc01_gr_idle" }, 61 { 0x84, "pc01_strmout_00" }, 62 { 0x85, "pc01_strmout_01" }, 63 { 0xde, "pc01_trast_00" }, 64 { 0xdf, "pc01_trast_01" }, 65 { 0xe0, "pc01_trast_02" }, 66 { 0xe1, "pc01_trast_03" }, 67 { 0xe4, "pc01_trast_04" }, 68 { 0xe5, "pc01_trast_05" }, 69 { 0x82, "pc01_vattr_00" }, 70 { 0x83, "pc01_vattr_01" }, 71 { 0x46, "pc01_vfetch_00", g84_vfetch_sources }, 72 { 0x47, "pc01_vfetch_01", g84_vfetch_sources }, 73 { 0x48, "pc01_vfetch_02", g84_vfetch_sources }, 74 { 0x49, "pc01_vfetch_03", g84_vfetch_sources }, 75 { 0x4a, "pc01_vfetch_04", g84_vfetch_sources }, 76 { 0x4b, "pc01_vfetch_05", g84_vfetch_sources }, 77 { 0x4c, "pc01_vfetch_06", g84_vfetch_sources }, 78 { 0x4d, "pc01_vfetch_07", g84_vfetch_sources }, 79 { 0x4e, "pc01_vfetch_08", g84_vfetch_sources }, 80 { 0x4f, "pc01_vfetch_09", g84_vfetch_sources }, 81 { 0x50, "pc01_vfetch_0a", g84_vfetch_sources }, 82 { 0x51, "pc01_vfetch_0b", g84_vfetch_sources }, 83 { 0x52, "pc01_vfetch_0c", g84_vfetch_sources }, 84 { 0x53, "pc01_vfetch_0d", g84_vfetch_sources }, 85 { 0x54, "pc01_vfetch_0e", g84_vfetch_sources }, 86 { 0x55, "pc01_vfetch_0f", g84_vfetch_sources }, 87 { 0x56, "pc01_vfetch_10", g84_vfetch_sources }, 88 { 0x57, "pc01_vfetch_11", g84_vfetch_sources }, 89 { 0x58, "pc01_vfetch_12", g84_vfetch_sources }, 90 { 0x59, "pc01_vfetch_13", g84_vfetch_sources }, 91 { 0x5a, "pc01_vfetch_14", g84_vfetch_sources }, 92 { 0x5b, "pc01_vfetch_15", g84_vfetch_sources }, 93 { 0x5c, "pc01_vfetch_16", g84_vfetch_sources }, 94 { 0x5d, "pc01_vfetch_17", g84_vfetch_sources }, 95 { 0x5e, "pc01_vfetch_18", g84_vfetch_sources }, 96 { 0x5f, "pc01_vfetch_19", g84_vfetch_sources }, 97 { 0x07, "pc01_zcull_00", nv50_zcull_sources }, 98 { 0x08, "pc01_zcull_01", nv50_zcull_sources }, 99 { 0x09, "pc01_zcull_02", nv50_zcull_sources }, 100 { 0x0a, "pc01_zcull_03", nv50_zcull_sources }, 101 { 0x0b, "pc01_zcull_04", nv50_zcull_sources }, 102 { 0x0c, "pc01_zcull_05", nv50_zcull_sources }, 103 104 { 0xb0, "pc01_unk00" }, 105 { 0xec, "pc01_trailer" }, 106 {} 107 }, &nv40_perfctr_func }, 108 { 0xf0, (const struct nvkm_specsig[]) { 109 { 0x55, "pc02_crop_00", gt200_crop_sources }, 110 { 0x56, "pc02_crop_01", gt200_crop_sources }, 111 { 0x57, "pc02_crop_02", gt200_crop_sources }, 112 { 0x58, "pc02_crop_03", gt200_crop_sources }, 113 { 0x00, "pc02_prop_00", gt200_prop_sources }, 114 { 0x01, "pc02_prop_01", gt200_prop_sources }, 115 { 0x02, "pc02_prop_02", gt200_prop_sources }, 116 { 0x03, "pc02_prop_03", gt200_prop_sources }, 117 { 0x04, "pc02_prop_04", gt200_prop_sources }, 118 { 0x05, "pc02_prop_05", gt200_prop_sources }, 119 { 0x06, "pc02_prop_06", gt200_prop_sources }, 120 { 0x07, "pc02_prop_07", gt200_prop_sources }, 121 { 0x78, "pc02_tex_00", gt200_tex_sources }, 122 { 0x79, "pc02_tex_01", gt200_tex_sources }, 123 { 0x7a, "pc02_tex_02", gt200_tex_sources }, 124 { 0x7b, "pc02_tex_03", gt200_tex_sources }, 125 { 0x32, "pc02_tex_04", gt200_tex_sources }, 126 { 0x33, "pc02_tex_05", gt200_tex_sources }, 127 { 0x34, "pc02_tex_06", gt200_tex_sources }, 128 { 0x74, "pc02_zrop_00", nv50_zrop_sources }, 129 { 0x75, "pc02_zrop_01", nv50_zrop_sources }, 130 { 0x76, "pc02_zrop_02", nv50_zrop_sources }, 131 { 0x77, "pc02_zrop_03", nv50_zrop_sources }, 132 { 0xec, "pc02_trailer" }, 133 {} 134 }, &nv40_perfctr_func }, 135 { 0x20, (const struct nvkm_specsig[]) { 136 {} 137 }, &nv40_perfctr_func }, 138 { 0x20, (const struct nvkm_specsig[]) { 139 {} 140 }, &nv40_perfctr_func }, 141 { 0x20, (const struct nvkm_specsig[]) { 142 {} 143 }, &nv40_perfctr_func }, 144 { 0x20, (const struct nvkm_specsig[]) { 145 {} 146 }, &nv40_perfctr_func }, 147 { 0x20, (const struct nvkm_specsig[]) { 148 {} 149 }, &nv40_perfctr_func }, 150 {} 151 }; 152 153 int 154 gt200_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) 155 { 156 return nv40_pm_new_(gt200_pm, device, type, inst, ppm); 157 } 158