1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <engine/mpeg.h> 25 26 #include <subdev/bar.h> 27 #include <subdev/timer.h> 28 29 struct nv50_mpeg_chan { 30 struct nvkm_mpeg_chan base; 31 }; 32 33 /******************************************************************************* 34 * MPEG object classes 35 ******************************************************************************/ 36 37 static int 38 nv50_mpeg_object_ctor(struct nvkm_object *parent, 39 struct nvkm_object *engine, 40 struct nvkm_oclass *oclass, void *data, u32 size, 41 struct nvkm_object **pobject) 42 { 43 struct nvkm_gpuobj *obj; 44 int ret; 45 46 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, 47 16, 16, 0, &obj); 48 *pobject = nv_object(obj); 49 if (ret) 50 return ret; 51 52 nv_wo32(obj, 0x00, nv_mclass(obj)); 53 nv_wo32(obj, 0x04, 0x00000000); 54 nv_wo32(obj, 0x08, 0x00000000); 55 nv_wo32(obj, 0x0c, 0x00000000); 56 return 0; 57 } 58 59 struct nvkm_ofuncs 60 nv50_mpeg_ofuncs = { 61 .ctor = nv50_mpeg_object_ctor, 62 .dtor = _nvkm_gpuobj_dtor, 63 .init = _nvkm_gpuobj_init, 64 .fini = _nvkm_gpuobj_fini, 65 .rd32 = _nvkm_gpuobj_rd32, 66 .wr32 = _nvkm_gpuobj_wr32, 67 }; 68 69 static struct nvkm_oclass 70 nv50_mpeg_sclass[] = { 71 { 0x3174, &nv50_mpeg_ofuncs }, 72 {} 73 }; 74 75 /******************************************************************************* 76 * PMPEG context 77 ******************************************************************************/ 78 79 int 80 nv50_mpeg_context_ctor(struct nvkm_object *parent, 81 struct nvkm_object *engine, 82 struct nvkm_oclass *oclass, void *data, u32 size, 83 struct nvkm_object **pobject) 84 { 85 struct nvkm_bar *bar = nvkm_bar(parent); 86 struct nv50_mpeg_chan *chan; 87 int ret; 88 89 ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4, 90 0, NVOBJ_FLAG_ZERO_ALLOC, &chan); 91 *pobject = nv_object(chan); 92 if (ret) 93 return ret; 94 95 nv_wo32(chan, 0x0070, 0x00801ec1); 96 nv_wo32(chan, 0x007c, 0x0000037c); 97 bar->flush(bar); 98 return 0; 99 } 100 101 static struct nvkm_oclass 102 nv50_mpeg_cclass = { 103 .handle = NV_ENGCTX(MPEG, 0x50), 104 .ofuncs = &(struct nvkm_ofuncs) { 105 .ctor = nv50_mpeg_context_ctor, 106 .dtor = _nvkm_mpeg_context_dtor, 107 .init = _nvkm_mpeg_context_init, 108 .fini = _nvkm_mpeg_context_fini, 109 .rd32 = _nvkm_mpeg_context_rd32, 110 .wr32 = _nvkm_mpeg_context_wr32, 111 }, 112 }; 113 114 /******************************************************************************* 115 * PMPEG engine/subdev functions 116 ******************************************************************************/ 117 118 void 119 nv50_mpeg_intr(struct nvkm_subdev *subdev) 120 { 121 struct nvkm_mpeg *mpeg = (void *)subdev; 122 struct nvkm_device *device = mpeg->engine.subdev.device; 123 u32 stat = nvkm_rd32(device, 0x00b100); 124 u32 type = nvkm_rd32(device, 0x00b230); 125 u32 mthd = nvkm_rd32(device, 0x00b234); 126 u32 data = nvkm_rd32(device, 0x00b238); 127 u32 show = stat; 128 129 if (stat & 0x01000000) { 130 /* happens on initial binding of the object */ 131 if (type == 0x00000020 && mthd == 0x0000) { 132 nvkm_wr32(device, 0x00b308, 0x00000100); 133 show &= ~0x01000000; 134 } 135 } 136 137 if (show) { 138 nv_info(mpeg, "0x%08x 0x%08x 0x%08x 0x%08x\n", 139 stat, type, mthd, data); 140 } 141 142 nvkm_wr32(device, 0x00b100, stat); 143 nvkm_wr32(device, 0x00b230, 0x00000001); 144 } 145 146 static void 147 nv50_vpe_intr(struct nvkm_subdev *subdev) 148 { 149 struct nvkm_mpeg *mpeg = (void *)subdev; 150 struct nvkm_device *device = mpeg->engine.subdev.device; 151 152 if (nvkm_rd32(device, 0x00b100)) 153 nv50_mpeg_intr(subdev); 154 155 if (nvkm_rd32(device, 0x00b800)) { 156 u32 stat = nvkm_rd32(device, 0x00b800); 157 nv_info(mpeg, "PMSRCH: 0x%08x\n", stat); 158 nvkm_wr32(device, 0xb800, stat); 159 } 160 } 161 162 static int 163 nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 164 struct nvkm_oclass *oclass, void *data, u32 size, 165 struct nvkm_object **pobject) 166 { 167 struct nvkm_mpeg *mpeg; 168 int ret; 169 170 ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg); 171 *pobject = nv_object(mpeg); 172 if (ret) 173 return ret; 174 175 nv_subdev(mpeg)->unit = 0x00400002; 176 nv_subdev(mpeg)->intr = nv50_vpe_intr; 177 nv_engine(mpeg)->cclass = &nv50_mpeg_cclass; 178 nv_engine(mpeg)->sclass = nv50_mpeg_sclass; 179 return 0; 180 } 181 182 int 183 nv50_mpeg_init(struct nvkm_object *object) 184 { 185 struct nvkm_mpeg *mpeg = (void *)object; 186 struct nvkm_device *device = mpeg->engine.subdev.device; 187 int ret; 188 189 ret = nvkm_mpeg_init(mpeg); 190 if (ret) 191 return ret; 192 193 nvkm_wr32(device, 0x00b32c, 0x00000000); 194 nvkm_wr32(device, 0x00b314, 0x00000100); 195 nvkm_wr32(device, 0x00b0e0, 0x0000001a); 196 197 nvkm_wr32(device, 0x00b220, 0x00000044); 198 nvkm_wr32(device, 0x00b300, 0x00801ec1); 199 nvkm_wr32(device, 0x00b390, 0x00000000); 200 nvkm_wr32(device, 0x00b394, 0x00000000); 201 nvkm_wr32(device, 0x00b398, 0x00000000); 202 nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001); 203 204 nvkm_wr32(device, 0x00b100, 0xffffffff); 205 nvkm_wr32(device, 0x00b140, 0xffffffff); 206 207 if (nvkm_msec(device, 2000, 208 if (!(nvkm_rd32(device, 0x00b200) & 0x00000001)) 209 break; 210 ) < 0) { 211 nv_error(mpeg, "timeout 0x%08x\n", nvkm_rd32(device, 0x00b200)); 212 return -EBUSY; 213 } 214 215 return 0; 216 } 217 218 struct nvkm_oclass 219 nv50_mpeg_oclass = { 220 .handle = NV_ENGINE(MPEG, 0x50), 221 .ofuncs = &(struct nvkm_ofuncs) { 222 .ctor = nv50_mpeg_ctor, 223 .dtor = _nvkm_mpeg_dtor, 224 .init = nv50_mpeg_init, 225 .fini = _nvkm_mpeg_fini, 226 }, 227 }; 228