1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <engine/mpeg.h> 25 26 #include <subdev/timer.h> 27 28 struct nv50_mpeg_chan { 29 struct nvkm_mpeg_chan base; 30 }; 31 32 /******************************************************************************* 33 * MPEG object classes 34 ******************************************************************************/ 35 36 static int 37 nv50_mpeg_object_ctor(struct nvkm_object *parent, 38 struct nvkm_object *engine, 39 struct nvkm_oclass *oclass, void *data, u32 size, 40 struct nvkm_object **pobject) 41 { 42 struct nvkm_gpuobj *obj; 43 int ret; 44 45 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, 46 16, 16, 0, &obj); 47 *pobject = nv_object(obj); 48 if (ret) 49 return ret; 50 51 nvkm_kmap(obj); 52 nvkm_wo32(obj, 0x00, nv_mclass(obj)); 53 nvkm_wo32(obj, 0x04, 0x00000000); 54 nvkm_wo32(obj, 0x08, 0x00000000); 55 nvkm_wo32(obj, 0x0c, 0x00000000); 56 nvkm_done(obj); 57 return 0; 58 } 59 60 struct nvkm_ofuncs 61 nv50_mpeg_ofuncs = { 62 .ctor = nv50_mpeg_object_ctor, 63 .dtor = _nvkm_gpuobj_dtor, 64 .init = _nvkm_gpuobj_init, 65 .fini = _nvkm_gpuobj_fini, 66 .rd32 = _nvkm_gpuobj_rd32, 67 .wr32 = _nvkm_gpuobj_wr32, 68 }; 69 70 static struct nvkm_oclass 71 nv50_mpeg_sclass[] = { 72 { 0x3174, &nv50_mpeg_ofuncs }, 73 {} 74 }; 75 76 /******************************************************************************* 77 * PMPEG context 78 ******************************************************************************/ 79 80 int 81 nv50_mpeg_context_ctor(struct nvkm_object *parent, 82 struct nvkm_object *engine, 83 struct nvkm_oclass *oclass, void *data, u32 size, 84 struct nvkm_object **pobject) 85 { 86 struct nv50_mpeg_chan *chan; 87 struct nvkm_gpuobj *image; 88 int ret; 89 90 ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4, 91 0, NVOBJ_FLAG_ZERO_ALLOC, &chan); 92 *pobject = nv_object(chan); 93 if (ret) 94 return ret; 95 96 image = &chan->base.base.gpuobj; 97 98 nvkm_kmap(image); 99 nvkm_wo32(image, 0x0070, 0x00801ec1); 100 nvkm_wo32(image, 0x007c, 0x0000037c); 101 nvkm_done(image); 102 return 0; 103 } 104 105 static struct nvkm_oclass 106 nv50_mpeg_cclass = { 107 .handle = NV_ENGCTX(MPEG, 0x50), 108 .ofuncs = &(struct nvkm_ofuncs) { 109 .ctor = nv50_mpeg_context_ctor, 110 .dtor = _nvkm_mpeg_context_dtor, 111 .init = _nvkm_mpeg_context_init, 112 .fini = _nvkm_mpeg_context_fini, 113 .rd32 = _nvkm_mpeg_context_rd32, 114 .wr32 = _nvkm_mpeg_context_wr32, 115 }, 116 }; 117 118 /******************************************************************************* 119 * PMPEG engine/subdev functions 120 ******************************************************************************/ 121 122 void 123 nv50_mpeg_intr(struct nvkm_subdev *subdev) 124 { 125 struct nvkm_mpeg *mpeg = (void *)subdev; 126 struct nvkm_device *device = mpeg->engine.subdev.device; 127 u32 stat = nvkm_rd32(device, 0x00b100); 128 u32 type = nvkm_rd32(device, 0x00b230); 129 u32 mthd = nvkm_rd32(device, 0x00b234); 130 u32 data = nvkm_rd32(device, 0x00b238); 131 u32 show = stat; 132 133 if (stat & 0x01000000) { 134 /* happens on initial binding of the object */ 135 if (type == 0x00000020 && mthd == 0x0000) { 136 nvkm_wr32(device, 0x00b308, 0x00000100); 137 show &= ~0x01000000; 138 } 139 } 140 141 if (show) { 142 nvkm_info(subdev, "%08x %08x %08x %08x\n", 143 stat, type, mthd, data); 144 } 145 146 nvkm_wr32(device, 0x00b100, stat); 147 nvkm_wr32(device, 0x00b230, 0x00000001); 148 } 149 150 static void 151 nv50_vpe_intr(struct nvkm_subdev *subdev) 152 { 153 struct nvkm_device *device = subdev->device; 154 155 if (nvkm_rd32(device, 0x00b100)) 156 nv50_mpeg_intr(subdev); 157 158 if (nvkm_rd32(device, 0x00b800)) { 159 u32 stat = nvkm_rd32(device, 0x00b800); 160 nvkm_info(subdev, "PMSRCH: %08x\n", stat); 161 nvkm_wr32(device, 0xb800, stat); 162 } 163 } 164 165 static int 166 nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 167 struct nvkm_oclass *oclass, void *data, u32 size, 168 struct nvkm_object **pobject) 169 { 170 struct nvkm_mpeg *mpeg; 171 int ret; 172 173 ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg); 174 *pobject = nv_object(mpeg); 175 if (ret) 176 return ret; 177 178 nv_subdev(mpeg)->unit = 0x00400002; 179 nv_subdev(mpeg)->intr = nv50_vpe_intr; 180 nv_engine(mpeg)->cclass = &nv50_mpeg_cclass; 181 nv_engine(mpeg)->sclass = nv50_mpeg_sclass; 182 return 0; 183 } 184 185 int 186 nv50_mpeg_init(struct nvkm_object *object) 187 { 188 struct nvkm_mpeg *mpeg = (void *)object; 189 struct nvkm_subdev *subdev = &mpeg->engine.subdev; 190 struct nvkm_device *device = subdev->device; 191 int ret; 192 193 ret = nvkm_mpeg_init(mpeg); 194 if (ret) 195 return ret; 196 197 nvkm_wr32(device, 0x00b32c, 0x00000000); 198 nvkm_wr32(device, 0x00b314, 0x00000100); 199 nvkm_wr32(device, 0x00b0e0, 0x0000001a); 200 201 nvkm_wr32(device, 0x00b220, 0x00000044); 202 nvkm_wr32(device, 0x00b300, 0x00801ec1); 203 nvkm_wr32(device, 0x00b390, 0x00000000); 204 nvkm_wr32(device, 0x00b394, 0x00000000); 205 nvkm_wr32(device, 0x00b398, 0x00000000); 206 nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001); 207 208 nvkm_wr32(device, 0x00b100, 0xffffffff); 209 nvkm_wr32(device, 0x00b140, 0xffffffff); 210 211 if (nvkm_msec(device, 2000, 212 if (!(nvkm_rd32(device, 0x00b200) & 0x00000001)) 213 break; 214 ) < 0) { 215 nvkm_error(subdev, "timeout %08x\n", 216 nvkm_rd32(device, 0x00b200)); 217 return -EBUSY; 218 } 219 220 return 0; 221 } 222 223 struct nvkm_oclass 224 nv50_mpeg_oclass = { 225 .handle = NV_ENGINE(MPEG, 0x50), 226 .ofuncs = &(struct nvkm_ofuncs) { 227 .ctor = nv50_mpeg_ctor, 228 .dtor = _nvkm_mpeg_dtor, 229 .init = nv50_mpeg_init, 230 .fini = _nvkm_mpeg_fini, 231 }, 232 }; 233