1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #define nv44_mpeg(p) container_of((p), struct nv44_mpeg, base.engine) 25 #include "priv.h" 26 27 #include <core/client.h> 28 #include <engine/fifo.h> 29 30 #include <nvif/class.h> 31 32 struct nv44_mpeg { 33 struct nvkm_mpeg base; 34 struct list_head chan; 35 }; 36 37 bool nv40_mpeg_mthd_dma(struct nvkm_device *, u32, u32); 38 39 /******************************************************************************* 40 * PMPEG context 41 ******************************************************************************/ 42 #define nv44_mpeg_chan(p) container_of((p), struct nv44_mpeg_chan, object) 43 44 struct nv44_mpeg_chan { 45 struct nvkm_object object; 46 struct nv44_mpeg *mpeg; 47 struct nvkm_fifo_chan *fifo; 48 struct list_head head; 49 u32 inst; 50 }; 51 52 static int 53 nv44_mpeg_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, 54 int align, struct nvkm_gpuobj **pgpuobj) 55 { 56 struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object); 57 int ret = nvkm_gpuobj_new(chan->object.engine->subdev.device, 264 * 4, 58 align, true, parent, pgpuobj); 59 if (ret == 0) { 60 chan->inst = (*pgpuobj)->addr; 61 nvkm_kmap(*pgpuobj); 62 nvkm_wo32(*pgpuobj, 0x78, 0x02001ec1); 63 nvkm_done(*pgpuobj); 64 } 65 return ret; 66 } 67 68 static int 69 nv44_mpeg_chan_fini(struct nvkm_object *object, bool suspend) 70 { 71 72 struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object); 73 struct nv44_mpeg *mpeg = chan->mpeg; 74 struct nvkm_device *device = mpeg->base.engine.subdev.device; 75 u32 inst = 0x80000000 | (chan->inst >> 4); 76 77 nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000000); 78 if (nvkm_rd32(device, 0x00b318) == inst) 79 nvkm_mask(device, 0x00b318, 0x80000000, 0x00000000); 80 nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001); 81 return 0; 82 } 83 84 static void * 85 nv44_mpeg_chan_dtor(struct nvkm_object *object) 86 { 87 struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object); 88 struct nv44_mpeg *mpeg = chan->mpeg; 89 unsigned long flags; 90 spin_lock_irqsave(&mpeg->base.engine.lock, flags); 91 list_del(&chan->head); 92 spin_unlock_irqrestore(&mpeg->base.engine.lock, flags); 93 return chan; 94 } 95 96 static const struct nvkm_object_func 97 nv44_mpeg_chan = { 98 .dtor = nv44_mpeg_chan_dtor, 99 .fini = nv44_mpeg_chan_fini, 100 .bind = nv44_mpeg_chan_bind, 101 }; 102 103 static int 104 nv44_mpeg_chan_new(struct nvkm_fifo_chan *fifoch, 105 const struct nvkm_oclass *oclass, 106 struct nvkm_object **pobject) 107 { 108 struct nv44_mpeg *mpeg = nv44_mpeg(oclass->engine); 109 struct nv44_mpeg_chan *chan; 110 unsigned long flags; 111 112 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 113 return -ENOMEM; 114 nvkm_object_ctor(&nv44_mpeg_chan, oclass, &chan->object); 115 chan->mpeg = mpeg; 116 chan->fifo = fifoch; 117 *pobject = &chan->object; 118 119 spin_lock_irqsave(&mpeg->base.engine.lock, flags); 120 list_add(&chan->head, &mpeg->chan); 121 spin_unlock_irqrestore(&mpeg->base.engine.lock, flags); 122 return 0; 123 } 124 125 /******************************************************************************* 126 * PMPEG engine/subdev functions 127 ******************************************************************************/ 128 129 static bool 130 nv44_mpeg_mthd(struct nvkm_device *device, u32 mthd, u32 data) 131 { 132 switch (mthd) { 133 case 0x190: 134 case 0x1a0: 135 case 0x1b0: 136 return nv40_mpeg_mthd_dma(device, mthd, data); 137 default: 138 break; 139 } 140 return false; 141 } 142 143 static void 144 nv44_mpeg_intr(struct nvkm_subdev *subdev) 145 { 146 struct nv44_mpeg *mpeg = (void *)subdev; 147 struct nv44_mpeg_chan *temp, *chan = NULL; 148 struct nvkm_device *device = mpeg->base.engine.subdev.device; 149 unsigned long flags; 150 u32 inst = nvkm_rd32(device, 0x00b318) & 0x000fffff; 151 u32 stat = nvkm_rd32(device, 0x00b100); 152 u32 type = nvkm_rd32(device, 0x00b230); 153 u32 mthd = nvkm_rd32(device, 0x00b234); 154 u32 data = nvkm_rd32(device, 0x00b238); 155 u32 show = stat; 156 157 spin_lock_irqsave(&mpeg->base.engine.lock, flags); 158 list_for_each_entry(temp, &mpeg->chan, head) { 159 if (temp->inst >> 4 == inst) { 160 chan = temp; 161 list_del(&chan->head); 162 list_add(&chan->head, &mpeg->chan); 163 break; 164 } 165 } 166 167 if (stat & 0x01000000) { 168 /* happens on initial binding of the object */ 169 if (type == 0x00000020 && mthd == 0x0000) { 170 nvkm_mask(device, 0x00b308, 0x00000000, 0x00000000); 171 show &= ~0x01000000; 172 } 173 174 if (type == 0x00000010) { 175 if (!nv44_mpeg_mthd(subdev->device, mthd, data)) 176 show &= ~0x01000000; 177 } 178 } 179 180 nvkm_wr32(device, 0x00b100, stat); 181 nvkm_wr32(device, 0x00b230, 0x00000001); 182 183 if (show) { 184 nvkm_error(subdev, "ch %d [%08x %s] %08x %08x %08x %08x\n", 185 chan ? chan->fifo->chid : -1, inst << 4, 186 chan ? chan->object.client->name : "unknown", 187 stat, type, mthd, data); 188 } 189 190 spin_unlock_irqrestore(&mpeg->base.engine.lock, flags); 191 } 192 193 static void 194 nv44_mpeg_me_intr(struct nvkm_subdev *subdev) 195 { 196 struct nvkm_mpeg *mpeg = (void *)subdev; 197 struct nvkm_device *device = mpeg->engine.subdev.device; 198 u32 stat; 199 200 if ((stat = nvkm_rd32(device, 0x00b100))) 201 nv44_mpeg_intr(subdev); 202 203 if ((stat = nvkm_rd32(device, 0x00b800))) { 204 nvkm_error(subdev, "PMSRCH %08x\n", stat); 205 nvkm_wr32(device, 0x00b800, stat); 206 } 207 } 208 209 static const struct nvkm_engine_func 210 nv44_mpeg = { 211 .fifo.cclass = nv44_mpeg_chan_new, 212 .sclass = { 213 { -1, -1, NV31_MPEG, &nv31_mpeg_object }, 214 {} 215 } 216 }; 217 218 static int 219 nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 220 struct nvkm_oclass *oclass, void *data, u32 size, 221 struct nvkm_object **pobject) 222 { 223 struct nv44_mpeg *mpeg; 224 int ret; 225 226 ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg); 227 *pobject = nv_object(mpeg); 228 if (ret) 229 return ret; 230 231 INIT_LIST_HEAD(&mpeg->chan); 232 mpeg->base.engine.func = &nv44_mpeg; 233 234 nv_subdev(mpeg)->unit = 0x00000002; 235 nv_subdev(mpeg)->intr = nv44_mpeg_me_intr; 236 nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog; 237 return 0; 238 } 239 240 struct nvkm_oclass 241 nv44_mpeg_oclass = { 242 .handle = NV_ENGINE(MPEG, 0x44), 243 .ofuncs = &(struct nvkm_ofuncs) { 244 .ctor = nv44_mpeg_ctor, 245 .dtor = _nvkm_mpeg_dtor, 246 .init = nv31_mpeg_init, 247 .fini = _nvkm_mpeg_fini, 248 }, 249 }; 250