1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "nv31.h"
25 
26 #include <subdev/instmem.h>
27 
28 #include <nvif/class.h>
29 
30 bool
31 nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
32 {
33 	struct nvkm_instmem *imem = device->imem;
34 	u32 inst = data << 4;
35 	u32 dma0 = nvkm_instmem_rd32(imem, inst + 0);
36 	u32 dma1 = nvkm_instmem_rd32(imem, inst + 4);
37 	u32 dma2 = nvkm_instmem_rd32(imem, inst + 8);
38 	u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
39 	u32 size = dma1 + 1;
40 
41 	/* only allow linear DMA objects */
42 	if (!(dma0 & 0x00002000))
43 		return false;
44 
45 	if (mthd == 0x0190) {
46 		/* DMA_CMD */
47 		nvkm_mask(device, 0x00b300, 0x00030000, (dma0 & 0x00030000));
48 		nvkm_wr32(device, 0x00b334, base);
49 		nvkm_wr32(device, 0x00b324, size);
50 	} else
51 	if (mthd == 0x01a0) {
52 		/* DMA_DATA */
53 		nvkm_mask(device, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
54 		nvkm_wr32(device, 0x00b360, base);
55 		nvkm_wr32(device, 0x00b364, size);
56 	} else {
57 		/* DMA_IMAGE, VRAM only */
58 		if (dma0 & 0x00030000)
59 			return false;
60 
61 		nvkm_wr32(device, 0x00b370, base);
62 		nvkm_wr32(device, 0x00b374, size);
63 	}
64 
65 	return true;
66 }
67 
68 static const struct nv31_mpeg_func
69 nv40_mpeg = {
70 	.mthd_dma = nv40_mpeg_mthd_dma,
71 };
72 
73 int
74 nv40_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
75 {
76 	return nv31_mpeg_new_(&nv40_mpeg, device, index, pmpeg);
77 }
78