1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "nv31.h"
25 
26 #include <subdev/instmem.h>
27 
28 /*******************************************************************************
29  * MPEG object classes
30  ******************************************************************************/
31 
32 static int
33 nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
34 {
35 	struct nv31_mpeg *mpeg = (void *)object->engine;
36 	struct nvkm_device *device = mpeg->base.engine.subdev.device;
37 	struct nvkm_instmem *imem = device->imem;
38 	u32 inst = *(u32 *)arg << 4;
39 	u32 dma0 = nv_ro32(imem, inst + 0);
40 	u32 dma1 = nv_ro32(imem, inst + 4);
41 	u32 dma2 = nv_ro32(imem, inst + 8);
42 	u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
43 	u32 size = dma1 + 1;
44 
45 	/* only allow linear DMA objects */
46 	if (!(dma0 & 0x00002000))
47 		return -EINVAL;
48 
49 	if (mthd == 0x0190) {
50 		/* DMA_CMD */
51 		nvkm_mask(device, 0x00b300, 0x00030000, (dma0 & 0x00030000));
52 		nvkm_wr32(device, 0x00b334, base);
53 		nvkm_wr32(device, 0x00b324, size);
54 	} else
55 	if (mthd == 0x01a0) {
56 		/* DMA_DATA */
57 		nvkm_mask(device, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
58 		nvkm_wr32(device, 0x00b360, base);
59 		nvkm_wr32(device, 0x00b364, size);
60 	} else {
61 		/* DMA_IMAGE, VRAM only */
62 		if (dma0 & 0x00030000)
63 			return -EINVAL;
64 
65 		nvkm_wr32(device, 0x00b370, base);
66 		nvkm_wr32(device, 0x00b374, size);
67 	}
68 
69 	return 0;
70 }
71 
72 static struct nvkm_omthds
73 nv40_mpeg_omthds[] = {
74 	{ 0x0190, 0x0190, nv40_mpeg_mthd_dma },
75 	{ 0x01a0, 0x01a0, nv40_mpeg_mthd_dma },
76 	{ 0x01b0, 0x01b0, nv40_mpeg_mthd_dma },
77 	{}
78 };
79 
80 struct nvkm_oclass
81 nv40_mpeg_sclass[] = {
82 	{ 0x3174, &nv31_mpeg_ofuncs, nv40_mpeg_omthds },
83 	{}
84 };
85 
86 /*******************************************************************************
87  * PMPEG engine/subdev functions
88  ******************************************************************************/
89 
90 static void
91 nv40_mpeg_intr(struct nvkm_subdev *subdev)
92 {
93 	struct nv31_mpeg *mpeg = (void *)subdev;
94 	struct nvkm_device *device = mpeg->base.engine.subdev.device;
95 	u32 stat;
96 
97 	if ((stat = nvkm_rd32(device, 0x00b100)))
98 		nv31_mpeg_intr(subdev);
99 
100 	if ((stat = nvkm_rd32(device, 0x00b800))) {
101 		nv_error(mpeg, "PMSRCH 0x%08x\n", stat);
102 		nvkm_wr32(device, 0x00b800, stat);
103 	}
104 }
105 
106 static int
107 nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
108 	       struct nvkm_oclass *oclass, void *data, u32 size,
109 	       struct nvkm_object **pobject)
110 {
111 	struct nv31_mpeg *mpeg;
112 	int ret;
113 
114 	ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
115 	*pobject = nv_object(mpeg);
116 	if (ret)
117 		return ret;
118 
119 	nv_subdev(mpeg)->unit = 0x00000002;
120 	nv_subdev(mpeg)->intr = nv40_mpeg_intr;
121 	nv_engine(mpeg)->cclass = &nv31_mpeg_cclass;
122 	nv_engine(mpeg)->sclass = nv40_mpeg_sclass;
123 	nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
124 	return 0;
125 }
126 
127 struct nvkm_oclass
128 nv40_mpeg_oclass = {
129 	.handle = NV_ENGINE(MPEG, 0x40),
130 	.ofuncs = &(struct nvkm_ofuncs) {
131 		.ctor = nv40_mpeg_ctor,
132 		.dtor = _nvkm_mpeg_dtor,
133 		.init = nv31_mpeg_init,
134 		.fini = _nvkm_mpeg_fini,
135 	},
136 };
137