1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv31.h" 25 26 #include <subdev/instmem.h> 27 28 #include <nvif/class.h> 29 30 bool 31 nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) 32 { 33 struct nvkm_instmem *imem = device->imem; 34 u32 inst = data << 4; 35 u32 dma0 = nvkm_instmem_rd32(imem, inst + 0); 36 u32 dma1 = nvkm_instmem_rd32(imem, inst + 4); 37 u32 dma2 = nvkm_instmem_rd32(imem, inst + 8); 38 u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); 39 u32 size = dma1 + 1; 40 41 /* only allow linear DMA objects */ 42 if (!(dma0 & 0x00002000)) 43 return false; 44 45 if (mthd == 0x0190) { 46 /* DMA_CMD */ 47 nvkm_mask(device, 0x00b300, 0x00030000, (dma0 & 0x00030000)); 48 nvkm_wr32(device, 0x00b334, base); 49 nvkm_wr32(device, 0x00b324, size); 50 } else 51 if (mthd == 0x01a0) { 52 /* DMA_DATA */ 53 nvkm_mask(device, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2); 54 nvkm_wr32(device, 0x00b360, base); 55 nvkm_wr32(device, 0x00b364, size); 56 } else { 57 /* DMA_IMAGE, VRAM only */ 58 if (dma0 & 0x00030000) 59 return false; 60 61 nvkm_wr32(device, 0x00b370, base); 62 nvkm_wr32(device, 0x00b374, size); 63 } 64 65 return true; 66 } 67 68 static void 69 nv40_mpeg_intr(struct nvkm_subdev *subdev) 70 { 71 struct nv31_mpeg *mpeg = (void *)subdev; 72 struct nvkm_device *device = mpeg->base.engine.subdev.device; 73 u32 stat; 74 75 if ((stat = nvkm_rd32(device, 0x00b100))) 76 nv31_mpeg_intr(subdev); 77 78 if ((stat = nvkm_rd32(device, 0x00b800))) { 79 nvkm_error(subdev, "PMSRCH %08x\n", stat); 80 nvkm_wr32(device, 0x00b800, stat); 81 } 82 } 83 84 static const struct nvkm_engine_func 85 nv40_mpeg = { 86 .fifo.cclass = nv31_mpeg_chan_new, 87 .sclass = { 88 { -1, -1, NV31_MPEG, &nv31_mpeg_object }, 89 {} 90 } 91 }; 92 93 static int 94 nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 95 struct nvkm_oclass *oclass, void *data, u32 size, 96 struct nvkm_object **pobject) 97 { 98 struct nv31_mpeg *mpeg; 99 int ret; 100 101 ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg); 102 *pobject = nv_object(mpeg); 103 if (ret) 104 return ret; 105 106 mpeg->base.engine.func = &nv40_mpeg; 107 108 mpeg->mthd_dma = nv40_mpeg_mthd_dma; 109 nv_subdev(mpeg)->unit = 0x00000002; 110 nv_subdev(mpeg)->intr = nv40_mpeg_intr; 111 nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog; 112 return 0; 113 } 114 115 struct nvkm_oclass 116 nv40_mpeg_oclass = { 117 .handle = NV_ENGINE(MPEG, 0x40), 118 .ofuncs = &(struct nvkm_ofuncs) { 119 .ctor = nv40_mpeg_ctor, 120 .dtor = _nvkm_mpeg_dtor, 121 .init = nv31_mpeg_init, 122 .fini = _nvkm_mpeg_fini, 123 }, 124 }; 125