1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv31.h" 25 26 #include <core/client.h> 27 #include <core/handle.h> 28 #include <engine/fifo.h> 29 #include <subdev/instmem.h> 30 #include <subdev/fb.h> 31 #include <subdev/timer.h> 32 33 /******************************************************************************* 34 * MPEG object classes 35 ******************************************************************************/ 36 37 static int 38 nv31_mpeg_object_ctor(struct nvkm_object *parent, 39 struct nvkm_object *engine, 40 struct nvkm_oclass *oclass, void *data, u32 size, 41 struct nvkm_object **pobject) 42 { 43 struct nvkm_gpuobj *obj; 44 int ret; 45 46 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, 47 20, 16, 0, &obj); 48 *pobject = nv_object(obj); 49 if (ret) 50 return ret; 51 52 nv_wo32(obj, 0x00, nv_mclass(obj)); 53 nv_wo32(obj, 0x04, 0x00000000); 54 nv_wo32(obj, 0x08, 0x00000000); 55 nv_wo32(obj, 0x0c, 0x00000000); 56 return 0; 57 } 58 59 static int 60 nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len) 61 { 62 struct nvkm_instmem *imem = nvkm_instmem(object); 63 struct nv31_mpeg_priv *priv = (void *)object->engine; 64 u32 inst = *(u32 *)arg << 4; 65 u32 dma0 = nv_ro32(imem, inst + 0); 66 u32 dma1 = nv_ro32(imem, inst + 4); 67 u32 dma2 = nv_ro32(imem, inst + 8); 68 u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); 69 u32 size = dma1 + 1; 70 71 /* only allow linear DMA objects */ 72 if (!(dma0 & 0x00002000)) 73 return -EINVAL; 74 75 if (mthd == 0x0190) { 76 /* DMA_CMD */ 77 nv_mask(priv, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0); 78 nv_wr32(priv, 0x00b334, base); 79 nv_wr32(priv, 0x00b324, size); 80 } else 81 if (mthd == 0x01a0) { 82 /* DMA_DATA */ 83 nv_mask(priv, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0); 84 nv_wr32(priv, 0x00b360, base); 85 nv_wr32(priv, 0x00b364, size); 86 } else { 87 /* DMA_IMAGE, VRAM only */ 88 if (dma0 & 0x00030000) 89 return -EINVAL; 90 91 nv_wr32(priv, 0x00b370, base); 92 nv_wr32(priv, 0x00b374, size); 93 } 94 95 return 0; 96 } 97 98 struct nvkm_ofuncs 99 nv31_mpeg_ofuncs = { 100 .ctor = nv31_mpeg_object_ctor, 101 .dtor = _nvkm_gpuobj_dtor, 102 .init = _nvkm_gpuobj_init, 103 .fini = _nvkm_gpuobj_fini, 104 .rd32 = _nvkm_gpuobj_rd32, 105 .wr32 = _nvkm_gpuobj_wr32, 106 }; 107 108 static struct nvkm_omthds 109 nv31_mpeg_omthds[] = { 110 { 0x0190, 0x0190, nv31_mpeg_mthd_dma }, 111 { 0x01a0, 0x01a0, nv31_mpeg_mthd_dma }, 112 { 0x01b0, 0x01b0, nv31_mpeg_mthd_dma }, 113 {} 114 }; 115 116 struct nvkm_oclass 117 nv31_mpeg_sclass[] = { 118 { 0x3174, &nv31_mpeg_ofuncs, nv31_mpeg_omthds }, 119 {} 120 }; 121 122 /******************************************************************************* 123 * PMPEG context 124 ******************************************************************************/ 125 126 static int 127 nv31_mpeg_context_ctor(struct nvkm_object *parent, 128 struct nvkm_object *engine, 129 struct nvkm_oclass *oclass, void *data, u32 size, 130 struct nvkm_object **pobject) 131 { 132 struct nv31_mpeg_priv *priv = (void *)engine; 133 struct nv31_mpeg_chan *chan; 134 unsigned long flags; 135 int ret; 136 137 ret = nvkm_object_create(parent, engine, oclass, 0, &chan); 138 *pobject = nv_object(chan); 139 if (ret) 140 return ret; 141 142 spin_lock_irqsave(&nv_engine(priv)->lock, flags); 143 if (priv->chan) { 144 spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); 145 nvkm_object_destroy(&chan->base); 146 *pobject = NULL; 147 return -EBUSY; 148 } 149 priv->chan = chan; 150 spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); 151 return 0; 152 } 153 154 static void 155 nv31_mpeg_context_dtor(struct nvkm_object *object) 156 { 157 struct nv31_mpeg_priv *priv = (void *)object->engine; 158 struct nv31_mpeg_chan *chan = (void *)object; 159 unsigned long flags; 160 161 spin_lock_irqsave(&nv_engine(priv)->lock, flags); 162 priv->chan = NULL; 163 spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); 164 nvkm_object_destroy(&chan->base); 165 } 166 167 struct nvkm_oclass 168 nv31_mpeg_cclass = { 169 .handle = NV_ENGCTX(MPEG, 0x31), 170 .ofuncs = &(struct nvkm_ofuncs) { 171 .ctor = nv31_mpeg_context_ctor, 172 .dtor = nv31_mpeg_context_dtor, 173 .init = nvkm_object_init, 174 .fini = nvkm_object_fini, 175 }, 176 }; 177 178 /******************************************************************************* 179 * PMPEG engine/subdev functions 180 ******************************************************************************/ 181 182 void 183 nv31_mpeg_tile_prog(struct nvkm_engine *engine, int i) 184 { 185 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; 186 struct nv31_mpeg_priv *priv = (void *)engine; 187 188 nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch); 189 nv_wr32(priv, 0x00b004 + (i * 0x10), tile->limit); 190 nv_wr32(priv, 0x00b000 + (i * 0x10), tile->addr); 191 } 192 193 void 194 nv31_mpeg_intr(struct nvkm_subdev *subdev) 195 { 196 struct nv31_mpeg_priv *priv = (void *)subdev; 197 struct nvkm_fifo *pfifo = nvkm_fifo(subdev); 198 struct nvkm_handle *handle; 199 struct nvkm_object *engctx; 200 u32 stat = nv_rd32(priv, 0x00b100); 201 u32 type = nv_rd32(priv, 0x00b230); 202 u32 mthd = nv_rd32(priv, 0x00b234); 203 u32 data = nv_rd32(priv, 0x00b238); 204 u32 show = stat; 205 unsigned long flags; 206 207 spin_lock_irqsave(&nv_engine(priv)->lock, flags); 208 engctx = nv_object(priv->chan); 209 210 if (stat & 0x01000000) { 211 /* happens on initial binding of the object */ 212 if (type == 0x00000020 && mthd == 0x0000) { 213 nv_mask(priv, 0x00b308, 0x00000000, 0x00000000); 214 show &= ~0x01000000; 215 } 216 217 if (type == 0x00000010 && engctx) { 218 handle = nvkm_handle_get_class(engctx, 0x3174); 219 if (handle && !nv_call(handle->object, mthd, data)) 220 show &= ~0x01000000; 221 nvkm_handle_put(handle); 222 } 223 } 224 225 nv_wr32(priv, 0x00b100, stat); 226 nv_wr32(priv, 0x00b230, 0x00000001); 227 228 if (show) { 229 nv_error(priv, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n", 230 pfifo->chid(pfifo, engctx), 231 nvkm_client_name(engctx), stat, type, mthd, data); 232 } 233 234 spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); 235 } 236 237 static int 238 nv31_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 239 struct nvkm_oclass *oclass, void *data, u32 size, 240 struct nvkm_object **pobject) 241 { 242 struct nv31_mpeg_priv *priv; 243 int ret; 244 245 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); 246 *pobject = nv_object(priv); 247 if (ret) 248 return ret; 249 250 nv_subdev(priv)->unit = 0x00000002; 251 nv_subdev(priv)->intr = nv31_mpeg_intr; 252 nv_engine(priv)->cclass = &nv31_mpeg_cclass; 253 nv_engine(priv)->sclass = nv31_mpeg_sclass; 254 nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog; 255 return 0; 256 } 257 258 int 259 nv31_mpeg_init(struct nvkm_object *object) 260 { 261 struct nvkm_engine *engine = nv_engine(object); 262 struct nv31_mpeg_priv *priv = (void *)object; 263 struct nvkm_fb *pfb = nvkm_fb(object); 264 int ret, i; 265 266 ret = nvkm_mpeg_init(&priv->base); 267 if (ret) 268 return ret; 269 270 /* VPE init */ 271 nv_wr32(priv, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */ 272 nv_wr32(priv, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */ 273 274 for (i = 0; i < pfb->tile.regions; i++) 275 engine->tile_prog(engine, i); 276 277 /* PMPEG init */ 278 nv_wr32(priv, 0x00b32c, 0x00000000); 279 nv_wr32(priv, 0x00b314, 0x00000100); 280 nv_wr32(priv, 0x00b220, 0x00000031); 281 nv_wr32(priv, 0x00b300, 0x02001ec1); 282 nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); 283 284 nv_wr32(priv, 0x00b100, 0xffffffff); 285 nv_wr32(priv, 0x00b140, 0xffffffff); 286 287 if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) { 288 nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200)); 289 return -EBUSY; 290 } 291 292 return 0; 293 } 294 295 struct nvkm_oclass 296 nv31_mpeg_oclass = { 297 .handle = NV_ENGINE(MPEG, 0x31), 298 .ofuncs = &(struct nvkm_ofuncs) { 299 .ctor = nv31_mpeg_ctor, 300 .dtor = _nvkm_mpeg_dtor, 301 .init = nv31_mpeg_init, 302 .fini = _nvkm_mpeg_fini, 303 }, 304 }; 305