1 /* 2 * Copyright 2019 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "gf100.h" 23 #include "ctxgf100.h" 24 25 #include <nvif/class.h> 26 27 static void 28 tu102_gr_init_fecs_exceptions(struct gf100_gr *gr) 29 { 30 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006f0002); 31 } 32 33 static void 34 tu102_gr_init_fs(struct gf100_gr *gr) 35 { 36 struct nvkm_device *device = gr->base.engine.subdev.device; 37 int sm; 38 39 gp100_grctx_generate_smid_config(gr); 40 gk104_grctx_generate_gpc_tpc_nr(gr); 41 42 for (sm = 0; sm < gr->sm_nr; sm++) { 43 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + 44 gr->sm[sm].tpc * 4), sm); 45 } 46 47 gm200_grctx_generate_dist_skip_table(gr); 48 gf100_gr_init_num_tpc_per_gpc(gr, true, true); 49 } 50 51 static void 52 tu102_gr_init_zcull(struct gf100_gr *gr) 53 { 54 struct nvkm_device *device = gr->base.engine.subdev.device; 55 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); 56 const u8 tile_nr = ALIGN(gr->tpc_total, 64); 57 u8 bank[GPC_MAX] = {}, gpc, i, j; 58 u32 data; 59 60 for (i = 0; i < tile_nr; i += 8) { 61 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { 62 data |= bank[gr->tile[i + j]] << (j * 4); 63 bank[gr->tile[i + j]]++; 64 } 65 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data); 66 } 67 68 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 69 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), 70 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); 71 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | 72 gr->tpc_total); 73 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); 74 } 75 76 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); 77 } 78 79 static void 80 tu102_gr_init_gpc_mmu(struct gf100_gr *gr) 81 { 82 struct nvkm_device *device = gr->base.engine.subdev.device; 83 84 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff); 85 nvkm_wr32(device, 0x418890, 0x00000000); 86 nvkm_wr32(device, 0x418894, 0x00000000); 87 88 nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); 89 nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); 90 nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); 91 } 92 93 static const struct gf100_gr_func 94 tu102_gr = { 95 .oneinit_tiles = gm200_gr_oneinit_tiles, 96 .oneinit_sm_id = gm200_gr_oneinit_sm_id, 97 .init = gf100_gr_init, 98 .init_419bd8 = gv100_gr_init_419bd8, 99 .init_gpc_mmu = tu102_gr_init_gpc_mmu, 100 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, 101 .init_zcull = tu102_gr_init_zcull, 102 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs, 103 .init_rop_active_fbps = gp100_gr_init_rop_active_fbps, 104 .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask, 105 .init_fs = tu102_gr_init_fs, 106 .init_fecs_exceptions = tu102_gr_init_fecs_exceptions, 107 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2, 108 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, 109 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, 110 .init_504430 = gv100_gr_init_504430, 111 .init_shader_exceptions = gv100_gr_init_shader_exceptions, 112 .trap_mp = gv100_gr_trap_mp, 113 .rops = gm200_gr_rops, 114 .gpc_nr = 6, 115 .tpc_nr = 5, 116 .ppc_nr = 3, 117 .grctx = &tu102_grctx, 118 .zbc = &gp102_gr_zbc, 119 .sclass = { 120 { -1, -1, FERMI_TWOD_A }, 121 { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, 122 { -1, -1, TURING_A, &gf100_fermi }, 123 { -1, -1, TURING_COMPUTE_A }, 124 {} 125 } 126 }; 127 128 MODULE_FIRMWARE("nvidia/tu102/gr/fecs_bl.bin"); 129 MODULE_FIRMWARE("nvidia/tu102/gr/fecs_inst.bin"); 130 MODULE_FIRMWARE("nvidia/tu102/gr/fecs_data.bin"); 131 MODULE_FIRMWARE("nvidia/tu102/gr/fecs_sig.bin"); 132 MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_bl.bin"); 133 MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_inst.bin"); 134 MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_data.bin"); 135 MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_sig.bin"); 136 MODULE_FIRMWARE("nvidia/tu102/gr/sw_ctx.bin"); 137 MODULE_FIRMWARE("nvidia/tu102/gr/sw_nonctx.bin"); 138 MODULE_FIRMWARE("nvidia/tu102/gr/sw_bundle_init.bin"); 139 MODULE_FIRMWARE("nvidia/tu102/gr/sw_method_init.bin"); 140 141 MODULE_FIRMWARE("nvidia/tu104/gr/fecs_bl.bin"); 142 MODULE_FIRMWARE("nvidia/tu104/gr/fecs_inst.bin"); 143 MODULE_FIRMWARE("nvidia/tu104/gr/fecs_data.bin"); 144 MODULE_FIRMWARE("nvidia/tu104/gr/fecs_sig.bin"); 145 MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_bl.bin"); 146 MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_inst.bin"); 147 MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_data.bin"); 148 MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_sig.bin"); 149 MODULE_FIRMWARE("nvidia/tu104/gr/sw_ctx.bin"); 150 MODULE_FIRMWARE("nvidia/tu104/gr/sw_nonctx.bin"); 151 MODULE_FIRMWARE("nvidia/tu104/gr/sw_bundle_init.bin"); 152 MODULE_FIRMWARE("nvidia/tu104/gr/sw_method_init.bin"); 153 154 MODULE_FIRMWARE("nvidia/tu106/gr/fecs_bl.bin"); 155 MODULE_FIRMWARE("nvidia/tu106/gr/fecs_inst.bin"); 156 MODULE_FIRMWARE("nvidia/tu106/gr/fecs_data.bin"); 157 MODULE_FIRMWARE("nvidia/tu106/gr/fecs_sig.bin"); 158 MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_bl.bin"); 159 MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_inst.bin"); 160 MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_data.bin"); 161 MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_sig.bin"); 162 MODULE_FIRMWARE("nvidia/tu106/gr/sw_ctx.bin"); 163 MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin"); 164 MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin"); 165 MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin"); 166 167 MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin"); 168 MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin"); 169 MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin"); 170 MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin"); 171 MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin"); 172 MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin"); 173 MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin"); 174 MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin"); 175 MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin"); 176 MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin"); 177 MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin"); 178 MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin"); 179 180 MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin"); 181 MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin"); 182 MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin"); 183 MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin"); 184 MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin"); 185 MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin"); 186 MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin"); 187 MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin"); 188 MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin"); 189 MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin"); 190 MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin"); 191 MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin"); 192 193 static const struct gf100_gr_fwif 194 tu102_gr_fwif[] = { 195 { 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, 196 { -1, gm200_gr_nofw }, 197 {} 198 }; 199 200 int 201 tu102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) 202 { 203 return gf100_gr_new_(tu102_gr_fwif, device, type, inst, pgr); 204 } 205