1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv40.h" 25 #include "regs.h" 26 27 #include <core/client.h> 28 #include <core/gpuobj.h> 29 #include <subdev/fb.h> 30 #include <subdev/timer.h> 31 #include <engine/fifo.h> 32 33 u64 34 nv40_gr_units(struct nvkm_gr *gr) 35 { 36 return nvkm_rd32(gr->engine.subdev.device, 0x1540); 37 } 38 39 /******************************************************************************* 40 * Graphics object classes 41 ******************************************************************************/ 42 43 static int 44 nv40_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, 45 int align, struct nvkm_gpuobj **pgpuobj) 46 { 47 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 20, align, 48 false, parent, pgpuobj); 49 if (ret == 0) { 50 nvkm_kmap(*pgpuobj); 51 nvkm_wo32(*pgpuobj, 0x00, object->oclass); 52 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); 53 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); 54 #ifdef __BIG_ENDIAN 55 nvkm_mo32(*pgpuobj, 0x08, 0x01000000, 0x01000000); 56 #endif 57 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); 58 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); 59 nvkm_done(*pgpuobj); 60 } 61 return ret; 62 } 63 64 const struct nvkm_object_func 65 nv40_gr_object = { 66 .bind = nv40_gr_object_bind, 67 }; 68 69 /******************************************************************************* 70 * PGRAPH context 71 ******************************************************************************/ 72 73 static int 74 nv40_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, 75 int align, struct nvkm_gpuobj **pgpuobj) 76 { 77 struct nv40_gr_chan *chan = nv40_gr_chan(object); 78 struct nv40_gr *gr = chan->gr; 79 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, 80 align, true, parent, pgpuobj); 81 if (ret == 0) { 82 chan->inst = (*pgpuobj)->addr; 83 nvkm_kmap(*pgpuobj); 84 nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); 85 nvkm_wo32(*pgpuobj, 0x00000, chan->inst >> 4); 86 nvkm_done(*pgpuobj); 87 } 88 return ret; 89 } 90 91 static int 92 nv40_gr_chan_fini(struct nvkm_object *object, bool suspend) 93 { 94 struct nv40_gr_chan *chan = nv40_gr_chan(object); 95 struct nv40_gr *gr = chan->gr; 96 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 97 struct nvkm_device *device = subdev->device; 98 u32 inst = 0x01000000 | chan->inst >> 4; 99 int ret = 0; 100 101 nvkm_mask(device, 0x400720, 0x00000001, 0x00000000); 102 103 if (nvkm_rd32(device, 0x40032c) == inst) { 104 if (suspend) { 105 nvkm_wr32(device, 0x400720, 0x00000000); 106 nvkm_wr32(device, 0x400784, inst); 107 nvkm_mask(device, 0x400310, 0x00000020, 0x00000020); 108 nvkm_mask(device, 0x400304, 0x00000001, 0x00000001); 109 if (nvkm_msec(device, 2000, 110 if (!(nvkm_rd32(device, 0x400300) & 0x00000001)) 111 break; 112 ) < 0) { 113 u32 insn = nvkm_rd32(device, 0x400308); 114 nvkm_warn(subdev, "ctxprog timeout %08x\n", insn); 115 ret = -EBUSY; 116 } 117 } 118 119 nvkm_mask(device, 0x40032c, 0x01000000, 0x00000000); 120 } 121 122 if (nvkm_rd32(device, 0x400330) == inst) 123 nvkm_mask(device, 0x400330, 0x01000000, 0x00000000); 124 125 nvkm_mask(device, 0x400720, 0x00000001, 0x00000001); 126 return ret; 127 } 128 129 static void * 130 nv40_gr_chan_dtor(struct nvkm_object *object) 131 { 132 struct nv40_gr_chan *chan = nv40_gr_chan(object); 133 unsigned long flags; 134 spin_lock_irqsave(&chan->gr->base.engine.lock, flags); 135 list_del(&chan->head); 136 spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags); 137 return chan; 138 } 139 140 static const struct nvkm_object_func 141 nv40_gr_chan = { 142 .dtor = nv40_gr_chan_dtor, 143 .fini = nv40_gr_chan_fini, 144 .bind = nv40_gr_chan_bind, 145 }; 146 147 int 148 nv40_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, 149 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) 150 { 151 struct nv40_gr *gr = nv40_gr(base); 152 struct nv40_gr_chan *chan; 153 unsigned long flags; 154 155 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 156 return -ENOMEM; 157 nvkm_object_ctor(&nv40_gr_chan, oclass, &chan->object); 158 chan->gr = gr; 159 *pobject = &chan->object; 160 161 spin_lock_irqsave(&chan->gr->base.engine.lock, flags); 162 list_add(&chan->head, &gr->chan); 163 spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags); 164 return 0; 165 } 166 167 /******************************************************************************* 168 * PGRAPH engine/subdev functions 169 ******************************************************************************/ 170 171 static void 172 nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) 173 { 174 struct nv40_gr *gr = nv40_gr(base); 175 struct nvkm_device *device = gr->base.engine.subdev.device; 176 struct nvkm_fifo *fifo = device->fifo; 177 unsigned long flags; 178 179 nvkm_fifo_pause(fifo, &flags); 180 nv04_gr_idle(&gr->base); 181 182 switch (device->chipset) { 183 case 0x40: 184 case 0x41: 185 case 0x42: 186 case 0x43: 187 case 0x45: 188 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); 189 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); 190 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); 191 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); 192 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); 193 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); 194 switch (device->chipset) { 195 case 0x40: 196 case 0x45: 197 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); 198 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); 199 break; 200 case 0x41: 201 case 0x42: 202 case 0x43: 203 nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); 204 nvkm_wr32(device, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); 205 break; 206 default: 207 break; 208 } 209 break; 210 case 0x47: 211 case 0x49: 212 case 0x4b: 213 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); 214 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); 215 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); 216 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); 217 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); 218 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); 219 nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); 220 nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); 221 break; 222 default: 223 WARN_ON(1); 224 break; 225 } 226 227 nvkm_fifo_start(fifo, &flags); 228 } 229 230 void 231 nv40_gr_intr(struct nvkm_gr *base) 232 { 233 struct nv40_gr *gr = nv40_gr(base); 234 struct nv40_gr_chan *temp, *chan = NULL; 235 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 236 struct nvkm_device *device = subdev->device; 237 u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); 238 u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); 239 u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); 240 u32 inst = nvkm_rd32(device, 0x40032c) & 0x000fffff; 241 u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); 242 u32 subc = (addr & 0x00070000) >> 16; 243 u32 mthd = (addr & 0x00001ffc); 244 u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); 245 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff; 246 u32 show = stat; 247 char msg[128], src[128], sta[128]; 248 unsigned long flags; 249 250 spin_lock_irqsave(&gr->base.engine.lock, flags); 251 list_for_each_entry(temp, &gr->chan, head) { 252 if (temp->inst >> 4 == inst) { 253 chan = temp; 254 list_del(&chan->head); 255 list_add(&chan->head, &gr->chan); 256 break; 257 } 258 } 259 260 if (stat & NV_PGRAPH_INTR_ERROR) { 261 if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) { 262 nvkm_mask(device, 0x402000, 0, 0); 263 } 264 } 265 266 nvkm_wr32(device, NV03_PGRAPH_INTR, stat); 267 nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); 268 269 if (show) { 270 nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show); 271 nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource); 272 nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus); 273 nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] " 274 "nstatus %08x [%s] ch %d [%08x %s] subc %d " 275 "class %04x mthd %04x data %08x\n", 276 show, msg, nsource, src, nstatus, sta, 277 chan ? chan->fifo->chid : -1, inst << 4, 278 chan ? chan->fifo->object.client->name : "unknown", 279 subc, class, mthd, data); 280 } 281 282 spin_unlock_irqrestore(&gr->base.engine.lock, flags); 283 } 284 285 int 286 nv40_gr_init(struct nvkm_gr *base) 287 { 288 struct nv40_gr *gr = nv40_gr(base); 289 struct nvkm_device *device = gr->base.engine.subdev.device; 290 int ret, i, j; 291 u32 vramsz; 292 293 /* generate and upload context program */ 294 ret = nv40_grctx_init(device, &gr->size); 295 if (ret) 296 return ret; 297 298 /* No context present currently */ 299 nvkm_wr32(device, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); 300 301 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); 302 nvkm_wr32(device, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); 303 304 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); 305 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); 306 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); 307 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xe0de8055); 308 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); 309 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); 310 311 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100); 312 nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); 313 314 j = nvkm_rd32(device, 0x1540) & 0xff; 315 if (j) { 316 for (i = 0; !(j & 1); j >>= 1, i++) 317 ; 318 nvkm_wr32(device, 0x405000, i); 319 } 320 321 if (device->chipset == 0x40) { 322 nvkm_wr32(device, 0x4009b0, 0x83280fff); 323 nvkm_wr32(device, 0x4009b4, 0x000000a0); 324 } else { 325 nvkm_wr32(device, 0x400820, 0x83280eff); 326 nvkm_wr32(device, 0x400824, 0x000000a0); 327 } 328 329 switch (device->chipset) { 330 case 0x40: 331 case 0x45: 332 nvkm_wr32(device, 0x4009b8, 0x0078e366); 333 nvkm_wr32(device, 0x4009bc, 0x0000014c); 334 break; 335 case 0x41: 336 case 0x42: /* pciid also 0x00Cx */ 337 /* case 0x0120: XXX (pciid) */ 338 nvkm_wr32(device, 0x400828, 0x007596ff); 339 nvkm_wr32(device, 0x40082c, 0x00000108); 340 break; 341 case 0x43: 342 nvkm_wr32(device, 0x400828, 0x0072cb77); 343 nvkm_wr32(device, 0x40082c, 0x00000108); 344 break; 345 case 0x44: 346 case 0x46: /* G72 */ 347 case 0x4a: 348 case 0x4c: /* G7x-based C51 */ 349 case 0x4e: 350 nvkm_wr32(device, 0x400860, 0); 351 nvkm_wr32(device, 0x400864, 0); 352 break; 353 case 0x47: /* G70 */ 354 case 0x49: /* G71 */ 355 case 0x4b: /* G73 */ 356 nvkm_wr32(device, 0x400828, 0x07830610); 357 nvkm_wr32(device, 0x40082c, 0x0000016A); 358 break; 359 default: 360 break; 361 } 362 363 nvkm_wr32(device, 0x400b38, 0x2ffff800); 364 nvkm_wr32(device, 0x400b3c, 0x00006000); 365 366 /* Tiling related stuff. */ 367 switch (device->chipset) { 368 case 0x44: 369 case 0x4a: 370 nvkm_wr32(device, 0x400bc4, 0x1003d888); 371 nvkm_wr32(device, 0x400bbc, 0xb7a7b500); 372 break; 373 case 0x46: 374 nvkm_wr32(device, 0x400bc4, 0x0000e024); 375 nvkm_wr32(device, 0x400bbc, 0xb7a7b520); 376 break; 377 case 0x4c: 378 case 0x4e: 379 case 0x67: 380 nvkm_wr32(device, 0x400bc4, 0x1003d888); 381 nvkm_wr32(device, 0x400bbc, 0xb7a7b540); 382 break; 383 default: 384 break; 385 } 386 387 /* begin RAM config */ 388 vramsz = device->func->resource_size(device, 1) - 1; 389 switch (device->chipset) { 390 case 0x40: 391 nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); 392 nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); 393 nvkm_wr32(device, 0x4069A4, nvkm_rd32(device, 0x100200)); 394 nvkm_wr32(device, 0x4069A8, nvkm_rd32(device, 0x100204)); 395 nvkm_wr32(device, 0x400820, 0); 396 nvkm_wr32(device, 0x400824, 0); 397 nvkm_wr32(device, 0x400864, vramsz); 398 nvkm_wr32(device, 0x400868, vramsz); 399 break; 400 default: 401 switch (device->chipset) { 402 case 0x41: 403 case 0x42: 404 case 0x43: 405 case 0x45: 406 case 0x4e: 407 case 0x44: 408 case 0x4a: 409 nvkm_wr32(device, 0x4009F0, nvkm_rd32(device, 0x100200)); 410 nvkm_wr32(device, 0x4009F4, nvkm_rd32(device, 0x100204)); 411 break; 412 default: 413 nvkm_wr32(device, 0x400DF0, nvkm_rd32(device, 0x100200)); 414 nvkm_wr32(device, 0x400DF4, nvkm_rd32(device, 0x100204)); 415 break; 416 } 417 nvkm_wr32(device, 0x4069F0, nvkm_rd32(device, 0x100200)); 418 nvkm_wr32(device, 0x4069F4, nvkm_rd32(device, 0x100204)); 419 nvkm_wr32(device, 0x400840, 0); 420 nvkm_wr32(device, 0x400844, 0); 421 nvkm_wr32(device, 0x4008A0, vramsz); 422 nvkm_wr32(device, 0x4008A4, vramsz); 423 break; 424 } 425 426 return 0; 427 } 428 429 int 430 nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, 431 int index, struct nvkm_gr **pgr) 432 { 433 struct nv40_gr *gr; 434 435 if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) 436 return -ENOMEM; 437 *pgr = &gr->base; 438 INIT_LIST_HEAD(&gr->chan); 439 440 return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base); 441 } 442 443 static const struct nvkm_gr_func 444 nv40_gr = { 445 .init = nv40_gr_init, 446 .intr = nv40_gr_intr, 447 .tile = nv40_gr_tile, 448 .units = nv40_gr_units, 449 .chan_new = nv40_gr_chan_new, 450 .sclass = { 451 { -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */ 452 { -1, -1, 0x0019, &nv40_gr_object }, /* clip */ 453 { -1, -1, 0x0030, &nv40_gr_object }, /* null */ 454 { -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */ 455 { -1, -1, 0x0043, &nv40_gr_object }, /* rop */ 456 { -1, -1, 0x0044, &nv40_gr_object }, /* patt */ 457 { -1, -1, 0x004a, &nv40_gr_object }, /* gdi */ 458 { -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */ 459 { -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */ 460 { -1, -1, 0x0089, &nv40_gr_object }, /* sifm */ 461 { -1, -1, 0x008a, &nv40_gr_object }, /* ifc */ 462 { -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */ 463 { -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */ 464 { -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */ 465 { -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */ 466 { -1, -1, 0x4097, &nv40_gr_object }, /* curie */ 467 {} 468 } 469 }; 470 471 int 472 nv40_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) 473 { 474 return nv40_gr_new_(&nv40_gr, device, index, pgr); 475 } 476