1 // SPDX-License-Identifier: MIT
2 #include "nv20.h"
3 #include "regs.h"
4 
5 #include <core/gpuobj.h>
6 #include <engine/fifo.h>
7 #include <engine/fifo/chan.h>
8 
9 /*******************************************************************************
10  * PGRAPH context
11  ******************************************************************************/
12 
13 static const struct nvkm_object_func
14 nv35_gr_chan = {
15 	.dtor = nv20_gr_chan_dtor,
16 	.init = nv20_gr_chan_init,
17 	.fini = nv20_gr_chan_fini,
18 };
19 
20 static int
21 nv35_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
22 		 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
23 {
24 	struct nv20_gr *gr = nv20_gr(base);
25 	struct nv20_gr_chan *chan;
26 	int ret, i;
27 
28 	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
29 		return -ENOMEM;
30 	nvkm_object_ctor(&nv35_gr_chan, oclass, &chan->object);
31 	chan->gr = gr;
32 	chan->chid = fifoch->id;
33 	*pobject = &chan->object;
34 
35 	ret = nvkm_memory_new(gr->base.engine.subdev.device,
36 			      NVKM_MEM_TARGET_INST, 0x577c, 16, true,
37 			      &chan->inst);
38 	if (ret)
39 		return ret;
40 
41 	nvkm_kmap(chan->inst);
42 	nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
43 	nvkm_wo32(chan->inst, 0x040c, 0x00000101);
44 	nvkm_wo32(chan->inst, 0x0420, 0x00000111);
45 	nvkm_wo32(chan->inst, 0x0424, 0x00000060);
46 	nvkm_wo32(chan->inst, 0x0440, 0x00000080);
47 	nvkm_wo32(chan->inst, 0x0444, 0xffff0000);
48 	nvkm_wo32(chan->inst, 0x0448, 0x00000001);
49 	nvkm_wo32(chan->inst, 0x045c, 0x44400000);
50 	nvkm_wo32(chan->inst, 0x0488, 0xffff0000);
51 	for (i = 0x04dc; i < 0x04e4; i += 4)
52 		nvkm_wo32(chan->inst, i, 0x0fff0000);
53 	nvkm_wo32(chan->inst, 0x04e8, 0x00011100);
54 	for (i = 0x0504; i < 0x0544; i += 4)
55 		nvkm_wo32(chan->inst, i, 0x07ff0000);
56 	nvkm_wo32(chan->inst, 0x054c, 0x4b7fffff);
57 	nvkm_wo32(chan->inst, 0x0588, 0x00000080);
58 	nvkm_wo32(chan->inst, 0x058c, 0x30201000);
59 	nvkm_wo32(chan->inst, 0x0590, 0x70605040);
60 	nvkm_wo32(chan->inst, 0x0594, 0xb8a89888);
61 	nvkm_wo32(chan->inst, 0x0598, 0xf8e8d8c8);
62 	nvkm_wo32(chan->inst, 0x05ac, 0xb0000000);
63 	for (i = 0x0604; i < 0x0644; i += 4)
64 		nvkm_wo32(chan->inst, i, 0x00010588);
65 	for (i = 0x0644; i < 0x0684; i += 4)
66 		nvkm_wo32(chan->inst, i, 0x00030303);
67 	for (i = 0x06c4; i < 0x0704; i += 4)
68 		nvkm_wo32(chan->inst, i, 0x0008aae4);
69 	for (i = 0x0704; i < 0x0744; i += 4)
70 		nvkm_wo32(chan->inst, i, 0x01012000);
71 	for (i = 0x0744; i < 0x0784; i += 4)
72 		nvkm_wo32(chan->inst, i, 0x00080008);
73 	nvkm_wo32(chan->inst, 0x0860, 0x00040000);
74 	nvkm_wo32(chan->inst, 0x0864, 0x00010000);
75 	for (i = 0x0868; i < 0x0878; i += 4)
76 		nvkm_wo32(chan->inst, i, 0x00040004);
77 	for (i = 0x1f1c; i <= 0x308c ; i += 16) {
78 		nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
79 		nvkm_wo32(chan->inst, i + 4, 0x0436086c);
80 		nvkm_wo32(chan->inst, i + 8, 0x000c001b);
81 	}
82 	for (i = 0x30bc; i < 0x30cc; i += 4)
83 		nvkm_wo32(chan->inst, i, 0x0000ffff);
84 	nvkm_wo32(chan->inst, 0x3450, 0x3f800000);
85 	nvkm_wo32(chan->inst, 0x380c, 0x3f800000);
86 	nvkm_wo32(chan->inst, 0x3820, 0x3f800000);
87 	nvkm_wo32(chan->inst, 0x384c, 0x40000000);
88 	nvkm_wo32(chan->inst, 0x3850, 0x3f800000);
89 	nvkm_wo32(chan->inst, 0x3854, 0x3f000000);
90 	nvkm_wo32(chan->inst, 0x385c, 0x40000000);
91 	nvkm_wo32(chan->inst, 0x3860, 0x3f800000);
92 	nvkm_wo32(chan->inst, 0x3868, 0xbf800000);
93 	nvkm_wo32(chan->inst, 0x3870, 0xbf800000);
94 	nvkm_done(chan->inst);
95 	return 0;
96 }
97 
98 /*******************************************************************************
99  * PGRAPH engine/subdev functions
100  ******************************************************************************/
101 
102 static const struct nvkm_gr_func
103 nv35_gr = {
104 	.dtor = nv20_gr_dtor,
105 	.oneinit = nv20_gr_oneinit,
106 	.init = nv30_gr_init,
107 	.intr = nv20_gr_intr,
108 	.tile = nv20_gr_tile,
109 	.chan_new = nv35_gr_chan_new,
110 	.sclass = {
111 		{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
112 		{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
113 		{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
114 		{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
115 		{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
116 		{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
117 		{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
118 		{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
119 		{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
120 		{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
121 		{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
122 		{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
123 		{ -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */
124 		{ -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */
125 		{ -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */
126 		{ -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */
127 		{ -1, -1, 0x0497, &nv04_gr_object }, /* rankine */
128 		{ -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
129 		{}
130 	}
131 };
132 
133 int
134 nv35_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
135 {
136 	return nv20_gr_new_(&nv35_gr, device, type, inst, pgr);
137 }
138