1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <engine/fifo.h> 5 6 /******************************************************************************* 7 * Graphics object classes 8 ******************************************************************************/ 9 10 static struct nvkm_oclass 11 nv35_gr_sclass[] = { 12 { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ 13 { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ 14 { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ 15 { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ 16 { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ 17 { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ 18 { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ 19 { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ 20 { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ 21 { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ 22 { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ 23 { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ 24 { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ 25 { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ 26 { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ 27 { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ 28 { 0x0497, &nv04_gr_ofuncs, NULL }, /* rankine */ 29 {}, 30 }; 31 32 /******************************************************************************* 33 * PGRAPH context 34 ******************************************************************************/ 35 36 static int 37 nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 38 struct nvkm_oclass *oclass, void *data, u32 size, 39 struct nvkm_object **pobject) 40 { 41 struct nv20_gr_chan *chan; 42 struct nvkm_gpuobj *image; 43 int ret, i; 44 45 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c, 46 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); 47 *pobject = nv_object(chan); 48 if (ret) 49 return ret; 50 51 chan->chid = nvkm_fifo_chan(parent)->chid; 52 image = &chan->base.base.gpuobj; 53 54 nvkm_kmap(image); 55 nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); 56 nvkm_wo32(image, 0x040c, 0x00000101); 57 nvkm_wo32(image, 0x0420, 0x00000111); 58 nvkm_wo32(image, 0x0424, 0x00000060); 59 nvkm_wo32(image, 0x0440, 0x00000080); 60 nvkm_wo32(image, 0x0444, 0xffff0000); 61 nvkm_wo32(image, 0x0448, 0x00000001); 62 nvkm_wo32(image, 0x045c, 0x44400000); 63 nvkm_wo32(image, 0x0488, 0xffff0000); 64 for (i = 0x04dc; i < 0x04e4; i += 4) 65 nvkm_wo32(image, i, 0x0fff0000); 66 nvkm_wo32(image, 0x04e8, 0x00011100); 67 for (i = 0x0504; i < 0x0544; i += 4) 68 nvkm_wo32(image, i, 0x07ff0000); 69 nvkm_wo32(image, 0x054c, 0x4b7fffff); 70 nvkm_wo32(image, 0x0588, 0x00000080); 71 nvkm_wo32(image, 0x058c, 0x30201000); 72 nvkm_wo32(image, 0x0590, 0x70605040); 73 nvkm_wo32(image, 0x0594, 0xb8a89888); 74 nvkm_wo32(image, 0x0598, 0xf8e8d8c8); 75 nvkm_wo32(image, 0x05ac, 0xb0000000); 76 for (i = 0x0604; i < 0x0644; i += 4) 77 nvkm_wo32(image, i, 0x00010588); 78 for (i = 0x0644; i < 0x0684; i += 4) 79 nvkm_wo32(image, i, 0x00030303); 80 for (i = 0x06c4; i < 0x0704; i += 4) 81 nvkm_wo32(image, i, 0x0008aae4); 82 for (i = 0x0704; i < 0x0744; i += 4) 83 nvkm_wo32(image, i, 0x01012000); 84 for (i = 0x0744; i < 0x0784; i += 4) 85 nvkm_wo32(image, i, 0x00080008); 86 nvkm_wo32(image, 0x0860, 0x00040000); 87 nvkm_wo32(image, 0x0864, 0x00010000); 88 for (i = 0x0868; i < 0x0878; i += 4) 89 nvkm_wo32(image, i, 0x00040004); 90 for (i = 0x1f1c; i <= 0x308c ; i += 16) { 91 nvkm_wo32(image, i + 0, 0x10700ff9); 92 nvkm_wo32(image, i + 4, 0x0436086c); 93 nvkm_wo32(image, i + 8, 0x000c001b); 94 } 95 for (i = 0x30bc; i < 0x30cc; i += 4) 96 nvkm_wo32(image, i, 0x0000ffff); 97 nvkm_wo32(image, 0x3450, 0x3f800000); 98 nvkm_wo32(image, 0x380c, 0x3f800000); 99 nvkm_wo32(image, 0x3820, 0x3f800000); 100 nvkm_wo32(image, 0x384c, 0x40000000); 101 nvkm_wo32(image, 0x3850, 0x3f800000); 102 nvkm_wo32(image, 0x3854, 0x3f000000); 103 nvkm_wo32(image, 0x385c, 0x40000000); 104 nvkm_wo32(image, 0x3860, 0x3f800000); 105 nvkm_wo32(image, 0x3868, 0xbf800000); 106 nvkm_wo32(image, 0x3870, 0xbf800000); 107 nvkm_done(image); 108 return 0; 109 } 110 111 static struct nvkm_oclass 112 nv35_gr_cclass = { 113 .handle = NV_ENGCTX(GR, 0x35), 114 .ofuncs = &(struct nvkm_ofuncs) { 115 .ctor = nv35_gr_context_ctor, 116 .dtor = _nvkm_gr_context_dtor, 117 .init = nv20_gr_context_init, 118 .fini = nv20_gr_context_fini, 119 .rd32 = _nvkm_gr_context_rd32, 120 .wr32 = _nvkm_gr_context_wr32, 121 }, 122 }; 123 124 /******************************************************************************* 125 * PGRAPH engine/subdev functions 126 ******************************************************************************/ 127 128 static int 129 nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 130 struct nvkm_oclass *oclass, void *data, u32 size, 131 struct nvkm_object **pobject) 132 { 133 struct nv20_gr *gr; 134 int ret; 135 136 ret = nvkm_gr_create(parent, engine, oclass, true, &gr); 137 *pobject = nv_object(gr); 138 if (ret) 139 return ret; 140 141 ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, 142 NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); 143 if (ret) 144 return ret; 145 146 nv_subdev(gr)->unit = 0x00001000; 147 nv_subdev(gr)->intr = nv20_gr_intr; 148 nv_engine(gr)->cclass = &nv35_gr_cclass; 149 nv_engine(gr)->sclass = nv35_gr_sclass; 150 nv_engine(gr)->tile_prog = nv20_gr_tile_prog; 151 return 0; 152 } 153 154 struct nvkm_oclass 155 nv35_gr_oclass = { 156 .handle = NV_ENGINE(GR, 0x35), 157 .ofuncs = &(struct nvkm_ofuncs) { 158 .ctor = nv35_gr_ctor, 159 .dtor = nv20_gr_dtor, 160 .init = nv30_gr_init, 161 .fini = _nvkm_gr_fini, 162 }, 163 }; 164