1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <engine/fifo.h> 5 #include <engine/fifo/chan.h> 6 7 /******************************************************************************* 8 * PGRAPH context 9 ******************************************************************************/ 10 11 static const struct nvkm_object_func 12 nv35_gr_chan = { 13 .dtor = nv20_gr_chan_dtor, 14 .init = nv20_gr_chan_init, 15 .fini = nv20_gr_chan_fini, 16 }; 17 18 static int 19 nv35_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, 20 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) 21 { 22 struct nv20_gr *gr = nv20_gr(base); 23 struct nv20_gr_chan *chan; 24 int ret, i; 25 26 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 27 return -ENOMEM; 28 nvkm_object_ctor(&nv35_gr_chan, oclass, &chan->object); 29 chan->gr = gr; 30 chan->chid = fifoch->chid; 31 *pobject = &chan->object; 32 33 ret = nvkm_memory_new(gr->base.engine.subdev.device, 34 NVKM_MEM_TARGET_INST, 0x577c, 16, true, 35 &chan->inst); 36 if (ret) 37 return ret; 38 39 nvkm_kmap(chan->inst); 40 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); 41 nvkm_wo32(chan->inst, 0x040c, 0x00000101); 42 nvkm_wo32(chan->inst, 0x0420, 0x00000111); 43 nvkm_wo32(chan->inst, 0x0424, 0x00000060); 44 nvkm_wo32(chan->inst, 0x0440, 0x00000080); 45 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); 46 nvkm_wo32(chan->inst, 0x0448, 0x00000001); 47 nvkm_wo32(chan->inst, 0x045c, 0x44400000); 48 nvkm_wo32(chan->inst, 0x0488, 0xffff0000); 49 for (i = 0x04dc; i < 0x04e4; i += 4) 50 nvkm_wo32(chan->inst, i, 0x0fff0000); 51 nvkm_wo32(chan->inst, 0x04e8, 0x00011100); 52 for (i = 0x0504; i < 0x0544; i += 4) 53 nvkm_wo32(chan->inst, i, 0x07ff0000); 54 nvkm_wo32(chan->inst, 0x054c, 0x4b7fffff); 55 nvkm_wo32(chan->inst, 0x0588, 0x00000080); 56 nvkm_wo32(chan->inst, 0x058c, 0x30201000); 57 nvkm_wo32(chan->inst, 0x0590, 0x70605040); 58 nvkm_wo32(chan->inst, 0x0594, 0xb8a89888); 59 nvkm_wo32(chan->inst, 0x0598, 0xf8e8d8c8); 60 nvkm_wo32(chan->inst, 0x05ac, 0xb0000000); 61 for (i = 0x0604; i < 0x0644; i += 4) 62 nvkm_wo32(chan->inst, i, 0x00010588); 63 for (i = 0x0644; i < 0x0684; i += 4) 64 nvkm_wo32(chan->inst, i, 0x00030303); 65 for (i = 0x06c4; i < 0x0704; i += 4) 66 nvkm_wo32(chan->inst, i, 0x0008aae4); 67 for (i = 0x0704; i < 0x0744; i += 4) 68 nvkm_wo32(chan->inst, i, 0x01012000); 69 for (i = 0x0744; i < 0x0784; i += 4) 70 nvkm_wo32(chan->inst, i, 0x00080008); 71 nvkm_wo32(chan->inst, 0x0860, 0x00040000); 72 nvkm_wo32(chan->inst, 0x0864, 0x00010000); 73 for (i = 0x0868; i < 0x0878; i += 4) 74 nvkm_wo32(chan->inst, i, 0x00040004); 75 for (i = 0x1f1c; i <= 0x308c ; i += 16) { 76 nvkm_wo32(chan->inst, i + 0, 0x10700ff9); 77 nvkm_wo32(chan->inst, i + 4, 0x0436086c); 78 nvkm_wo32(chan->inst, i + 8, 0x000c001b); 79 } 80 for (i = 0x30bc; i < 0x30cc; i += 4) 81 nvkm_wo32(chan->inst, i, 0x0000ffff); 82 nvkm_wo32(chan->inst, 0x3450, 0x3f800000); 83 nvkm_wo32(chan->inst, 0x380c, 0x3f800000); 84 nvkm_wo32(chan->inst, 0x3820, 0x3f800000); 85 nvkm_wo32(chan->inst, 0x384c, 0x40000000); 86 nvkm_wo32(chan->inst, 0x3850, 0x3f800000); 87 nvkm_wo32(chan->inst, 0x3854, 0x3f000000); 88 nvkm_wo32(chan->inst, 0x385c, 0x40000000); 89 nvkm_wo32(chan->inst, 0x3860, 0x3f800000); 90 nvkm_wo32(chan->inst, 0x3868, 0xbf800000); 91 nvkm_wo32(chan->inst, 0x3870, 0xbf800000); 92 nvkm_done(chan->inst); 93 return 0; 94 } 95 96 /******************************************************************************* 97 * PGRAPH engine/subdev functions 98 ******************************************************************************/ 99 100 static const struct nvkm_gr_func 101 nv35_gr = { 102 .chan_new = nv35_gr_chan_new, 103 .sclass = { 104 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ 105 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ 106 { -1, -1, 0x0030, &nv04_gr_object }, /* null */ 107 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ 108 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ 109 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ 110 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ 111 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ 112 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ 113 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ 114 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ 115 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ 116 { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */ 117 { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */ 118 { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */ 119 { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */ 120 { -1, -1, 0x0497, &nv04_gr_object }, /* rankine */ 121 {} 122 } 123 }; 124 125 static int 126 nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 127 struct nvkm_oclass *oclass, void *data, u32 size, 128 struct nvkm_object **pobject) 129 { 130 struct nvkm_device *device = (void *)parent; 131 struct nv20_gr *gr; 132 int ret; 133 134 ret = nvkm_gr_create(parent, engine, oclass, true, &gr); 135 *pobject = nv_object(gr); 136 if (ret) 137 return ret; 138 139 gr->base.func = &nv35_gr; 140 141 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, 142 &gr->ctxtab); 143 if (ret) 144 return ret; 145 146 nv_subdev(gr)->unit = 0x00001000; 147 nv_subdev(gr)->intr = nv20_gr_intr; 148 nv_engine(gr)->tile_prog = nv20_gr_tile_prog; 149 return 0; 150 } 151 152 struct nvkm_oclass 153 nv35_gr_oclass = { 154 .handle = NV_ENGINE(GR, 0x35), 155 .ofuncs = &(struct nvkm_ofuncs) { 156 .ctor = nv35_gr_ctor, 157 .dtor = nv20_gr_dtor, 158 .init = nv30_gr_init, 159 .fini = _nvkm_gr_fini, 160 }, 161 }; 162