1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <engine/fifo.h> 5 #include <subdev/fb.h> 6 7 /******************************************************************************* 8 * Graphics object classes 9 ******************************************************************************/ 10 11 static struct nvkm_oclass 12 nv30_gr_sclass[] = { 13 { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ 14 { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ 15 { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ 16 { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ 17 { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ 18 { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ 19 { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ 20 { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ 21 { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ 22 { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ 23 { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ 24 { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ 25 { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ 26 { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ 27 { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ 28 { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ 29 { 0x0397, &nv04_gr_ofuncs, NULL }, /* rankine */ 30 {}, 31 }; 32 33 /******************************************************************************* 34 * PGRAPH context 35 ******************************************************************************/ 36 37 static int 38 nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 39 struct nvkm_oclass *oclass, void *data, u32 size, 40 struct nvkm_object **pobject) 41 { 42 struct nv20_gr_chan *chan; 43 struct nvkm_gpuobj *image; 44 int ret, i; 45 46 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48, 47 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); 48 *pobject = nv_object(chan); 49 if (ret) 50 return ret; 51 52 chan->chid = nvkm_fifo_chan(parent)->chid; 53 image = &chan->base.base.gpuobj; 54 55 nvkm_kmap(image); 56 nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); 57 nvkm_wo32(image, 0x0410, 0x00000101); 58 nvkm_wo32(image, 0x0424, 0x00000111); 59 nvkm_wo32(image, 0x0428, 0x00000060); 60 nvkm_wo32(image, 0x0444, 0x00000080); 61 nvkm_wo32(image, 0x0448, 0xffff0000); 62 nvkm_wo32(image, 0x044c, 0x00000001); 63 nvkm_wo32(image, 0x0460, 0x44400000); 64 nvkm_wo32(image, 0x048c, 0xffff0000); 65 for (i = 0x04e0; i < 0x04e8; i += 4) 66 nvkm_wo32(image, i, 0x0fff0000); 67 nvkm_wo32(image, 0x04ec, 0x00011100); 68 for (i = 0x0508; i < 0x0548; i += 4) 69 nvkm_wo32(image, i, 0x07ff0000); 70 nvkm_wo32(image, 0x0550, 0x4b7fffff); 71 nvkm_wo32(image, 0x058c, 0x00000080); 72 nvkm_wo32(image, 0x0590, 0x30201000); 73 nvkm_wo32(image, 0x0594, 0x70605040); 74 nvkm_wo32(image, 0x0598, 0xb8a89888); 75 nvkm_wo32(image, 0x059c, 0xf8e8d8c8); 76 nvkm_wo32(image, 0x05b0, 0xb0000000); 77 for (i = 0x0600; i < 0x0640; i += 4) 78 nvkm_wo32(image, i, 0x00010588); 79 for (i = 0x0640; i < 0x0680; i += 4) 80 nvkm_wo32(image, i, 0x00030303); 81 for (i = 0x06c0; i < 0x0700; i += 4) 82 nvkm_wo32(image, i, 0x0008aae4); 83 for (i = 0x0700; i < 0x0740; i += 4) 84 nvkm_wo32(image, i, 0x01012000); 85 for (i = 0x0740; i < 0x0780; i += 4) 86 nvkm_wo32(image, i, 0x00080008); 87 nvkm_wo32(image, 0x085c, 0x00040000); 88 nvkm_wo32(image, 0x0860, 0x00010000); 89 for (i = 0x0864; i < 0x0874; i += 4) 90 nvkm_wo32(image, i, 0x00040004); 91 for (i = 0x1f18; i <= 0x3088 ; i += 16) { 92 nvkm_wo32(image, i + 0, 0x10700ff9); 93 nvkm_wo32(image, i + 1, 0x0436086c); 94 nvkm_wo32(image, i + 2, 0x000c001b); 95 } 96 for (i = 0x30b8; i < 0x30c8; i += 4) 97 nvkm_wo32(image, i, 0x0000ffff); 98 nvkm_wo32(image, 0x344c, 0x3f800000); 99 nvkm_wo32(image, 0x3808, 0x3f800000); 100 nvkm_wo32(image, 0x381c, 0x3f800000); 101 nvkm_wo32(image, 0x3848, 0x40000000); 102 nvkm_wo32(image, 0x384c, 0x3f800000); 103 nvkm_wo32(image, 0x3850, 0x3f000000); 104 nvkm_wo32(image, 0x3858, 0x40000000); 105 nvkm_wo32(image, 0x385c, 0x3f800000); 106 nvkm_wo32(image, 0x3864, 0xbf800000); 107 nvkm_wo32(image, 0x386c, 0xbf800000); 108 nvkm_done(image); 109 return 0; 110 } 111 112 static struct nvkm_oclass 113 nv30_gr_cclass = { 114 .handle = NV_ENGCTX(GR, 0x30), 115 .ofuncs = &(struct nvkm_ofuncs) { 116 .ctor = nv30_gr_context_ctor, 117 .dtor = _nvkm_gr_context_dtor, 118 .init = nv20_gr_context_init, 119 .fini = nv20_gr_context_fini, 120 .rd32 = _nvkm_gr_context_rd32, 121 .wr32 = _nvkm_gr_context_wr32, 122 }, 123 }; 124 125 /******************************************************************************* 126 * PGRAPH engine/subdev functions 127 ******************************************************************************/ 128 129 static int 130 nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 131 struct nvkm_oclass *oclass, void *data, u32 size, 132 struct nvkm_object **pobject) 133 { 134 struct nv20_gr *gr; 135 int ret; 136 137 ret = nvkm_gr_create(parent, engine, oclass, true, &gr); 138 *pobject = nv_object(gr); 139 if (ret) 140 return ret; 141 142 ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, 143 NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); 144 if (ret) 145 return ret; 146 147 nv_subdev(gr)->unit = 0x00001000; 148 nv_subdev(gr)->intr = nv20_gr_intr; 149 nv_engine(gr)->cclass = &nv30_gr_cclass; 150 nv_engine(gr)->sclass = nv30_gr_sclass; 151 nv_engine(gr)->tile_prog = nv20_gr_tile_prog; 152 return 0; 153 } 154 155 int 156 nv30_gr_init(struct nvkm_object *object) 157 { 158 struct nvkm_engine *engine = nv_engine(object); 159 struct nv20_gr *gr = (void *)engine; 160 struct nvkm_device *device = gr->base.engine.subdev.device; 161 struct nvkm_fb *fb = device->fb; 162 int ret, i; 163 164 ret = nvkm_gr_init(&gr->base); 165 if (ret) 166 return ret; 167 168 nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); 169 170 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); 171 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 172 173 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); 174 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); 175 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); 176 nvkm_wr32(device, 0x400890, 0x01b463ff); 177 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475); 178 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); 179 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); 180 nvkm_wr32(device, 0x400B80, 0x1003d888); 181 nvkm_wr32(device, 0x400B84, 0x0c000000); 182 nvkm_wr32(device, 0x400098, 0x00000000); 183 nvkm_wr32(device, 0x40009C, 0x0005ad00); 184 nvkm_wr32(device, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ 185 nvkm_wr32(device, 0x4000a0, 0x00000000); 186 nvkm_wr32(device, 0x4000a4, 0x00000008); 187 nvkm_wr32(device, 0x4008a8, 0xb784a400); 188 nvkm_wr32(device, 0x400ba0, 0x002f8685); 189 nvkm_wr32(device, 0x400ba4, 0x00231f3f); 190 nvkm_wr32(device, 0x4008a4, 0x40000020); 191 192 if (nv_device(gr)->chipset == 0x34) { 193 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); 194 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201); 195 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); 196 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000008); 197 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); 198 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000032); 199 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00004); 200 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000002); 201 } 202 203 nvkm_wr32(device, 0x4000c0, 0x00000016); 204 205 /* Turn all the tiling regions off. */ 206 for (i = 0; i < fb->tile.regions; i++) 207 engine->tile_prog(engine, i); 208 209 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 210 nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); 211 nvkm_wr32(device, 0x0040075c , 0x00000001); 212 213 /* begin RAM config */ 214 /* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */ 215 nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); 216 nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); 217 if (nv_device(gr)->chipset != 0x34) { 218 nvkm_wr32(device, 0x400750, 0x00EA0000); 219 nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200)); 220 nvkm_wr32(device, 0x400750, 0x00EA0004); 221 nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204)); 222 } 223 return 0; 224 } 225 226 struct nvkm_oclass 227 nv30_gr_oclass = { 228 .handle = NV_ENGINE(GR, 0x30), 229 .ofuncs = &(struct nvkm_ofuncs) { 230 .ctor = nv30_gr_ctor, 231 .dtor = nv20_gr_dtor, 232 .init = nv30_gr_init, 233 .fini = _nvkm_gr_fini, 234 }, 235 }; 236