1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <engine/fifo.h> 5 #include <subdev/fb.h> 6 7 /******************************************************************************* 8 * Graphics object classes 9 ******************************************************************************/ 10 11 static struct nvkm_oclass 12 nv30_gr_sclass[] = { 13 { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ 14 { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ 15 { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ 16 { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ 17 { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ 18 { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ 19 { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ 20 { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ 21 { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ 22 { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ 23 { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ 24 { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ 25 { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ 26 { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ 27 { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ 28 { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ 29 { 0x0397, &nv04_gr_ofuncs, NULL }, /* rankine */ 30 {}, 31 }; 32 33 /******************************************************************************* 34 * PGRAPH context 35 ******************************************************************************/ 36 37 static int 38 nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 39 struct nvkm_oclass *oclass, void *data, u32 size, 40 struct nvkm_object **pobject) 41 { 42 struct nv20_gr_chan *chan; 43 int ret, i; 44 45 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48, 46 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); 47 *pobject = nv_object(chan); 48 if (ret) 49 return ret; 50 51 chan->chid = nvkm_fifo_chan(parent)->chid; 52 53 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); 54 nv_wo32(chan, 0x0410, 0x00000101); 55 nv_wo32(chan, 0x0424, 0x00000111); 56 nv_wo32(chan, 0x0428, 0x00000060); 57 nv_wo32(chan, 0x0444, 0x00000080); 58 nv_wo32(chan, 0x0448, 0xffff0000); 59 nv_wo32(chan, 0x044c, 0x00000001); 60 nv_wo32(chan, 0x0460, 0x44400000); 61 nv_wo32(chan, 0x048c, 0xffff0000); 62 for (i = 0x04e0; i < 0x04e8; i += 4) 63 nv_wo32(chan, i, 0x0fff0000); 64 nv_wo32(chan, 0x04ec, 0x00011100); 65 for (i = 0x0508; i < 0x0548; i += 4) 66 nv_wo32(chan, i, 0x07ff0000); 67 nv_wo32(chan, 0x0550, 0x4b7fffff); 68 nv_wo32(chan, 0x058c, 0x00000080); 69 nv_wo32(chan, 0x0590, 0x30201000); 70 nv_wo32(chan, 0x0594, 0x70605040); 71 nv_wo32(chan, 0x0598, 0xb8a89888); 72 nv_wo32(chan, 0x059c, 0xf8e8d8c8); 73 nv_wo32(chan, 0x05b0, 0xb0000000); 74 for (i = 0x0600; i < 0x0640; i += 4) 75 nv_wo32(chan, i, 0x00010588); 76 for (i = 0x0640; i < 0x0680; i += 4) 77 nv_wo32(chan, i, 0x00030303); 78 for (i = 0x06c0; i < 0x0700; i += 4) 79 nv_wo32(chan, i, 0x0008aae4); 80 for (i = 0x0700; i < 0x0740; i += 4) 81 nv_wo32(chan, i, 0x01012000); 82 for (i = 0x0740; i < 0x0780; i += 4) 83 nv_wo32(chan, i, 0x00080008); 84 nv_wo32(chan, 0x085c, 0x00040000); 85 nv_wo32(chan, 0x0860, 0x00010000); 86 for (i = 0x0864; i < 0x0874; i += 4) 87 nv_wo32(chan, i, 0x00040004); 88 for (i = 0x1f18; i <= 0x3088 ; i += 16) { 89 nv_wo32(chan, i + 0, 0x10700ff9); 90 nv_wo32(chan, i + 1, 0x0436086c); 91 nv_wo32(chan, i + 2, 0x000c001b); 92 } 93 for (i = 0x30b8; i < 0x30c8; i += 4) 94 nv_wo32(chan, i, 0x0000ffff); 95 nv_wo32(chan, 0x344c, 0x3f800000); 96 nv_wo32(chan, 0x3808, 0x3f800000); 97 nv_wo32(chan, 0x381c, 0x3f800000); 98 nv_wo32(chan, 0x3848, 0x40000000); 99 nv_wo32(chan, 0x384c, 0x3f800000); 100 nv_wo32(chan, 0x3850, 0x3f000000); 101 nv_wo32(chan, 0x3858, 0x40000000); 102 nv_wo32(chan, 0x385c, 0x3f800000); 103 nv_wo32(chan, 0x3864, 0xbf800000); 104 nv_wo32(chan, 0x386c, 0xbf800000); 105 return 0; 106 } 107 108 static struct nvkm_oclass 109 nv30_gr_cclass = { 110 .handle = NV_ENGCTX(GR, 0x30), 111 .ofuncs = &(struct nvkm_ofuncs) { 112 .ctor = nv30_gr_context_ctor, 113 .dtor = _nvkm_gr_context_dtor, 114 .init = nv20_gr_context_init, 115 .fini = nv20_gr_context_fini, 116 .rd32 = _nvkm_gr_context_rd32, 117 .wr32 = _nvkm_gr_context_wr32, 118 }, 119 }; 120 121 /******************************************************************************* 122 * PGRAPH engine/subdev functions 123 ******************************************************************************/ 124 125 static int 126 nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 127 struct nvkm_oclass *oclass, void *data, u32 size, 128 struct nvkm_object **pobject) 129 { 130 struct nv20_gr *gr; 131 int ret; 132 133 ret = nvkm_gr_create(parent, engine, oclass, true, &gr); 134 *pobject = nv_object(gr); 135 if (ret) 136 return ret; 137 138 ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, 139 NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); 140 if (ret) 141 return ret; 142 143 nv_subdev(gr)->unit = 0x00001000; 144 nv_subdev(gr)->intr = nv20_gr_intr; 145 nv_engine(gr)->cclass = &nv30_gr_cclass; 146 nv_engine(gr)->sclass = nv30_gr_sclass; 147 nv_engine(gr)->tile_prog = nv20_gr_tile_prog; 148 return 0; 149 } 150 151 int 152 nv30_gr_init(struct nvkm_object *object) 153 { 154 struct nvkm_engine *engine = nv_engine(object); 155 struct nv20_gr *gr = (void *)engine; 156 struct nvkm_device *device = gr->base.engine.subdev.device; 157 struct nvkm_fb *fb = device->fb; 158 int ret, i; 159 160 ret = nvkm_gr_init(&gr->base); 161 if (ret) 162 return ret; 163 164 nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); 165 166 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); 167 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 168 169 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); 170 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); 171 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); 172 nvkm_wr32(device, 0x400890, 0x01b463ff); 173 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475); 174 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); 175 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); 176 nvkm_wr32(device, 0x400B80, 0x1003d888); 177 nvkm_wr32(device, 0x400B84, 0x0c000000); 178 nvkm_wr32(device, 0x400098, 0x00000000); 179 nvkm_wr32(device, 0x40009C, 0x0005ad00); 180 nvkm_wr32(device, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ 181 nvkm_wr32(device, 0x4000a0, 0x00000000); 182 nvkm_wr32(device, 0x4000a4, 0x00000008); 183 nvkm_wr32(device, 0x4008a8, 0xb784a400); 184 nvkm_wr32(device, 0x400ba0, 0x002f8685); 185 nvkm_wr32(device, 0x400ba4, 0x00231f3f); 186 nvkm_wr32(device, 0x4008a4, 0x40000020); 187 188 if (nv_device(gr)->chipset == 0x34) { 189 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); 190 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201); 191 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); 192 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000008); 193 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); 194 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000032); 195 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00004); 196 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000002); 197 } 198 199 nvkm_wr32(device, 0x4000c0, 0x00000016); 200 201 /* Turn all the tiling regions off. */ 202 for (i = 0; i < fb->tile.regions; i++) 203 engine->tile_prog(engine, i); 204 205 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 206 nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); 207 nvkm_wr32(device, 0x0040075c , 0x00000001); 208 209 /* begin RAM config */ 210 /* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */ 211 nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); 212 nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); 213 if (nv_device(gr)->chipset != 0x34) { 214 nvkm_wr32(device, 0x400750, 0x00EA0000); 215 nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200)); 216 nvkm_wr32(device, 0x400750, 0x00EA0004); 217 nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204)); 218 } 219 return 0; 220 } 221 222 struct nvkm_oclass 223 nv30_gr_oclass = { 224 .handle = NV_ENGINE(GR, 0x30), 225 .ofuncs = &(struct nvkm_ofuncs) { 226 .ctor = nv30_gr_ctor, 227 .dtor = nv20_gr_dtor, 228 .init = nv30_gr_init, 229 .fini = _nvkm_gr_fini, 230 }, 231 }; 232