1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <engine/fifo.h> 5 #include <engine/fifo/chan.h> 6 #include <subdev/fb.h> 7 8 /******************************************************************************* 9 * PGRAPH context 10 ******************************************************************************/ 11 12 static const struct nvkm_object_func 13 nv30_gr_chan = { 14 .dtor = nv20_gr_chan_dtor, 15 .init = nv20_gr_chan_init, 16 .fini = nv20_gr_chan_fini, 17 }; 18 19 static int 20 nv30_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, 21 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) 22 { 23 struct nv20_gr *gr = nv20_gr(base); 24 struct nv20_gr_chan *chan; 25 int ret, i; 26 27 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 28 return -ENOMEM; 29 nvkm_object_ctor(&nv30_gr_chan, oclass, &chan->object); 30 chan->gr = gr; 31 chan->chid = fifoch->chid; 32 *pobject = &chan->object; 33 34 ret = nvkm_memory_new(gr->base.engine.subdev.device, 35 NVKM_MEM_TARGET_INST, 0x5f48, 16, true, 36 &chan->inst); 37 if (ret) 38 return ret; 39 40 nvkm_kmap(chan->inst); 41 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); 42 nvkm_wo32(chan->inst, 0x0410, 0x00000101); 43 nvkm_wo32(chan->inst, 0x0424, 0x00000111); 44 nvkm_wo32(chan->inst, 0x0428, 0x00000060); 45 nvkm_wo32(chan->inst, 0x0444, 0x00000080); 46 nvkm_wo32(chan->inst, 0x0448, 0xffff0000); 47 nvkm_wo32(chan->inst, 0x044c, 0x00000001); 48 nvkm_wo32(chan->inst, 0x0460, 0x44400000); 49 nvkm_wo32(chan->inst, 0x048c, 0xffff0000); 50 for (i = 0x04e0; i < 0x04e8; i += 4) 51 nvkm_wo32(chan->inst, i, 0x0fff0000); 52 nvkm_wo32(chan->inst, 0x04ec, 0x00011100); 53 for (i = 0x0508; i < 0x0548; i += 4) 54 nvkm_wo32(chan->inst, i, 0x07ff0000); 55 nvkm_wo32(chan->inst, 0x0550, 0x4b7fffff); 56 nvkm_wo32(chan->inst, 0x058c, 0x00000080); 57 nvkm_wo32(chan->inst, 0x0590, 0x30201000); 58 nvkm_wo32(chan->inst, 0x0594, 0x70605040); 59 nvkm_wo32(chan->inst, 0x0598, 0xb8a89888); 60 nvkm_wo32(chan->inst, 0x059c, 0xf8e8d8c8); 61 nvkm_wo32(chan->inst, 0x05b0, 0xb0000000); 62 for (i = 0x0600; i < 0x0640; i += 4) 63 nvkm_wo32(chan->inst, i, 0x00010588); 64 for (i = 0x0640; i < 0x0680; i += 4) 65 nvkm_wo32(chan->inst, i, 0x00030303); 66 for (i = 0x06c0; i < 0x0700; i += 4) 67 nvkm_wo32(chan->inst, i, 0x0008aae4); 68 for (i = 0x0700; i < 0x0740; i += 4) 69 nvkm_wo32(chan->inst, i, 0x01012000); 70 for (i = 0x0740; i < 0x0780; i += 4) 71 nvkm_wo32(chan->inst, i, 0x00080008); 72 nvkm_wo32(chan->inst, 0x085c, 0x00040000); 73 nvkm_wo32(chan->inst, 0x0860, 0x00010000); 74 for (i = 0x0864; i < 0x0874; i += 4) 75 nvkm_wo32(chan->inst, i, 0x00040004); 76 for (i = 0x1f18; i <= 0x3088 ; i += 16) { 77 nvkm_wo32(chan->inst, i + 0, 0x10700ff9); 78 nvkm_wo32(chan->inst, i + 1, 0x0436086c); 79 nvkm_wo32(chan->inst, i + 2, 0x000c001b); 80 } 81 for (i = 0x30b8; i < 0x30c8; i += 4) 82 nvkm_wo32(chan->inst, i, 0x0000ffff); 83 nvkm_wo32(chan->inst, 0x344c, 0x3f800000); 84 nvkm_wo32(chan->inst, 0x3808, 0x3f800000); 85 nvkm_wo32(chan->inst, 0x381c, 0x3f800000); 86 nvkm_wo32(chan->inst, 0x3848, 0x40000000); 87 nvkm_wo32(chan->inst, 0x384c, 0x3f800000); 88 nvkm_wo32(chan->inst, 0x3850, 0x3f000000); 89 nvkm_wo32(chan->inst, 0x3858, 0x40000000); 90 nvkm_wo32(chan->inst, 0x385c, 0x3f800000); 91 nvkm_wo32(chan->inst, 0x3864, 0xbf800000); 92 nvkm_wo32(chan->inst, 0x386c, 0xbf800000); 93 nvkm_done(chan->inst); 94 return 0; 95 } 96 97 /******************************************************************************* 98 * PGRAPH engine/subdev functions 99 ******************************************************************************/ 100 101 static const struct nvkm_gr_func 102 nv30_gr = { 103 .chan_new = nv30_gr_chan_new, 104 .sclass = { 105 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ 106 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ 107 { -1, -1, 0x0030, &nv04_gr_object }, /* null */ 108 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ 109 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ 110 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ 111 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ 112 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ 113 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ 114 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ 115 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ 116 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ 117 { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */ 118 { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */ 119 { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */ 120 { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */ 121 { -1, -1, 0x0397, &nv04_gr_object }, /* rankine */ 122 {} 123 } 124 }; 125 126 static int 127 nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 128 struct nvkm_oclass *oclass, void *data, u32 size, 129 struct nvkm_object **pobject) 130 { 131 struct nvkm_device *device = (void *)parent; 132 struct nv20_gr *gr; 133 int ret; 134 135 ret = nvkm_gr_create(parent, engine, oclass, true, &gr); 136 *pobject = nv_object(gr); 137 if (ret) 138 return ret; 139 140 gr->base.func = &nv30_gr; 141 142 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, 143 &gr->ctxtab); 144 if (ret) 145 return ret; 146 147 nv_subdev(gr)->unit = 0x00001000; 148 nv_subdev(gr)->intr = nv20_gr_intr; 149 nv_engine(gr)->tile_prog = nv20_gr_tile_prog; 150 return 0; 151 } 152 153 int 154 nv30_gr_init(struct nvkm_object *object) 155 { 156 struct nvkm_engine *engine = nv_engine(object); 157 struct nv20_gr *gr = (void *)engine; 158 struct nvkm_device *device = gr->base.engine.subdev.device; 159 struct nvkm_fb *fb = device->fb; 160 int ret, i; 161 162 ret = nvkm_gr_init(&gr->base); 163 if (ret) 164 return ret; 165 166 nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, 167 nvkm_memory_addr(gr->ctxtab) >> 4); 168 169 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); 170 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 171 172 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); 173 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); 174 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); 175 nvkm_wr32(device, 0x400890, 0x01b463ff); 176 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475); 177 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); 178 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); 179 nvkm_wr32(device, 0x400B80, 0x1003d888); 180 nvkm_wr32(device, 0x400B84, 0x0c000000); 181 nvkm_wr32(device, 0x400098, 0x00000000); 182 nvkm_wr32(device, 0x40009C, 0x0005ad00); 183 nvkm_wr32(device, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ 184 nvkm_wr32(device, 0x4000a0, 0x00000000); 185 nvkm_wr32(device, 0x4000a4, 0x00000008); 186 nvkm_wr32(device, 0x4008a8, 0xb784a400); 187 nvkm_wr32(device, 0x400ba0, 0x002f8685); 188 nvkm_wr32(device, 0x400ba4, 0x00231f3f); 189 nvkm_wr32(device, 0x4008a4, 0x40000020); 190 191 if (nv_device(gr)->chipset == 0x34) { 192 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); 193 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201); 194 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); 195 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000008); 196 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); 197 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000032); 198 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00004); 199 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000002); 200 } 201 202 nvkm_wr32(device, 0x4000c0, 0x00000016); 203 204 /* Turn all the tiling regions off. */ 205 for (i = 0; i < fb->tile.regions; i++) 206 engine->tile_prog(engine, i); 207 208 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 209 nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); 210 nvkm_wr32(device, 0x0040075c , 0x00000001); 211 212 /* begin RAM config */ 213 /* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */ 214 nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); 215 nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); 216 if (nv_device(gr)->chipset != 0x34) { 217 nvkm_wr32(device, 0x400750, 0x00EA0000); 218 nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200)); 219 nvkm_wr32(device, 0x400750, 0x00EA0004); 220 nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204)); 221 } 222 return 0; 223 } 224 225 struct nvkm_oclass 226 nv30_gr_oclass = { 227 .handle = NV_ENGINE(GR, 0x30), 228 .ofuncs = &(struct nvkm_ofuncs) { 229 .ctor = nv30_gr_ctor, 230 .dtor = nv20_gr_dtor, 231 .init = nv30_gr_init, 232 .fini = _nvkm_gr_fini, 233 }, 234 }; 235