1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <engine/fifo.h> 5 6 /******************************************************************************* 7 * PGRAPH context 8 ******************************************************************************/ 9 10 static int 11 nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 12 struct nvkm_oclass *oclass, void *data, u32 size, 13 struct nvkm_object **pobject) 14 { 15 struct nv20_gr_chan *chan; 16 int ret, i; 17 18 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0, 19 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); 20 *pobject = nv_object(chan); 21 if (ret) 22 return ret; 23 24 chan->chid = nvkm_fifo_chan(parent)->chid; 25 26 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); 27 nv_wo32(chan, 0x033c, 0xffff0000); 28 nv_wo32(chan, 0x03a0, 0x0fff0000); 29 nv_wo32(chan, 0x03a4, 0x0fff0000); 30 nv_wo32(chan, 0x047c, 0x00000101); 31 nv_wo32(chan, 0x0490, 0x00000111); 32 nv_wo32(chan, 0x04a8, 0x44400000); 33 for (i = 0x04d4; i <= 0x04e0; i += 4) 34 nv_wo32(chan, i, 0x00030303); 35 for (i = 0x04f4; i <= 0x0500; i += 4) 36 nv_wo32(chan, i, 0x00080000); 37 for (i = 0x050c; i <= 0x0518; i += 4) 38 nv_wo32(chan, i, 0x01012000); 39 for (i = 0x051c; i <= 0x0528; i += 4) 40 nv_wo32(chan, i, 0x000105b8); 41 for (i = 0x052c; i <= 0x0538; i += 4) 42 nv_wo32(chan, i, 0x00080008); 43 for (i = 0x055c; i <= 0x0598; i += 4) 44 nv_wo32(chan, i, 0x07ff0000); 45 nv_wo32(chan, 0x05a4, 0x4b7fffff); 46 nv_wo32(chan, 0x05fc, 0x00000001); 47 nv_wo32(chan, 0x0604, 0x00004000); 48 nv_wo32(chan, 0x0610, 0x00000001); 49 nv_wo32(chan, 0x0618, 0x00040000); 50 nv_wo32(chan, 0x061c, 0x00010000); 51 for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ 52 nv_wo32(chan, (i + 0), 0x10700ff9); 53 nv_wo32(chan, (i + 4), 0x0436086c); 54 nv_wo32(chan, (i + 8), 0x000c001b); 55 } 56 nv_wo32(chan, 0x269c, 0x3f800000); 57 nv_wo32(chan, 0x26b0, 0x3f800000); 58 nv_wo32(chan, 0x26dc, 0x40000000); 59 nv_wo32(chan, 0x26e0, 0x3f800000); 60 nv_wo32(chan, 0x26e4, 0x3f000000); 61 nv_wo32(chan, 0x26ec, 0x40000000); 62 nv_wo32(chan, 0x26f0, 0x3f800000); 63 nv_wo32(chan, 0x26f8, 0xbf800000); 64 nv_wo32(chan, 0x2700, 0xbf800000); 65 nv_wo32(chan, 0x3024, 0x000fe000); 66 nv_wo32(chan, 0x30a0, 0x000003f8); 67 nv_wo32(chan, 0x33fc, 0x002fe000); 68 for (i = 0x341c; i <= 0x3438; i += 4) 69 nv_wo32(chan, i, 0x001c527c); 70 return 0; 71 } 72 73 static struct nvkm_oclass 74 nv2a_gr_cclass = { 75 .handle = NV_ENGCTX(GR, 0x2a), 76 .ofuncs = &(struct nvkm_ofuncs) { 77 .ctor = nv2a_gr_context_ctor, 78 .dtor = _nvkm_gr_context_dtor, 79 .init = nv20_gr_context_init, 80 .fini = nv20_gr_context_fini, 81 .rd32 = _nvkm_gr_context_rd32, 82 .wr32 = _nvkm_gr_context_wr32, 83 }, 84 }; 85 86 /******************************************************************************* 87 * PGRAPH engine/subdev functions 88 ******************************************************************************/ 89 90 static int 91 nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 92 struct nvkm_oclass *oclass, void *data, u32 size, 93 struct nvkm_object **pobject) 94 { 95 struct nv20_gr_priv *priv; 96 int ret; 97 98 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); 99 *pobject = nv_object(priv); 100 if (ret) 101 return ret; 102 103 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, 104 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); 105 if (ret) 106 return ret; 107 108 nv_subdev(priv)->unit = 0x00001000; 109 nv_subdev(priv)->intr = nv20_gr_intr; 110 nv_engine(priv)->cclass = &nv2a_gr_cclass; 111 nv_engine(priv)->sclass = nv25_gr_sclass; 112 nv_engine(priv)->tile_prog = nv20_gr_tile_prog; 113 return 0; 114 } 115 116 struct nvkm_oclass 117 nv2a_gr_oclass = { 118 .handle = NV_ENGINE(GR, 0x2a), 119 .ofuncs = &(struct nvkm_ofuncs) { 120 .ctor = nv2a_gr_ctor, 121 .dtor = nv20_gr_dtor, 122 .init = nv20_gr_init, 123 .fini = _nvkm_gr_fini, 124 }, 125 }; 126