1 #include "nv20.h"
2 #include "regs.h"
3 
4 #include <engine/fifo.h>
5 
6 /*******************************************************************************
7  * PGRAPH context
8  ******************************************************************************/
9 
10 static int
11 nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
12 		     struct nvkm_oclass *oclass, void *data, u32 size,
13 		     struct nvkm_object **pobject)
14 {
15 	struct nv20_gr_chan *chan;
16 	struct nvkm_gpuobj *image;
17 	int ret, i;
18 
19 	ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0,
20 				     16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
21 	*pobject = nv_object(chan);
22 	if (ret)
23 		return ret;
24 
25 	chan->chid = nvkm_fifo_chan(parent)->chid;
26 	image = &chan->base.base.gpuobj;
27 
28 	nvkm_kmap(image);
29 	nvkm_wo32(image, 0x0000, 0x00000001 | (chan->chid << 24));
30 	nvkm_wo32(image, 0x033c, 0xffff0000);
31 	nvkm_wo32(image, 0x03a0, 0x0fff0000);
32 	nvkm_wo32(image, 0x03a4, 0x0fff0000);
33 	nvkm_wo32(image, 0x047c, 0x00000101);
34 	nvkm_wo32(image, 0x0490, 0x00000111);
35 	nvkm_wo32(image, 0x04a8, 0x44400000);
36 	for (i = 0x04d4; i <= 0x04e0; i += 4)
37 		nvkm_wo32(image, i, 0x00030303);
38 	for (i = 0x04f4; i <= 0x0500; i += 4)
39 		nvkm_wo32(image, i, 0x00080000);
40 	for (i = 0x050c; i <= 0x0518; i += 4)
41 		nvkm_wo32(image, i, 0x01012000);
42 	for (i = 0x051c; i <= 0x0528; i += 4)
43 		nvkm_wo32(image, i, 0x000105b8);
44 	for (i = 0x052c; i <= 0x0538; i += 4)
45 		nvkm_wo32(image, i, 0x00080008);
46 	for (i = 0x055c; i <= 0x0598; i += 4)
47 		nvkm_wo32(image, i, 0x07ff0000);
48 	nvkm_wo32(image, 0x05a4, 0x4b7fffff);
49 	nvkm_wo32(image, 0x05fc, 0x00000001);
50 	nvkm_wo32(image, 0x0604, 0x00004000);
51 	nvkm_wo32(image, 0x0610, 0x00000001);
52 	nvkm_wo32(image, 0x0618, 0x00040000);
53 	nvkm_wo32(image, 0x061c, 0x00010000);
54 	for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */
55 		nvkm_wo32(image, (i + 0), 0x10700ff9);
56 		nvkm_wo32(image, (i + 4), 0x0436086c);
57 		nvkm_wo32(image, (i + 8), 0x000c001b);
58 	}
59 	nvkm_wo32(image, 0x269c, 0x3f800000);
60 	nvkm_wo32(image, 0x26b0, 0x3f800000);
61 	nvkm_wo32(image, 0x26dc, 0x40000000);
62 	nvkm_wo32(image, 0x26e0, 0x3f800000);
63 	nvkm_wo32(image, 0x26e4, 0x3f000000);
64 	nvkm_wo32(image, 0x26ec, 0x40000000);
65 	nvkm_wo32(image, 0x26f0, 0x3f800000);
66 	nvkm_wo32(image, 0x26f8, 0xbf800000);
67 	nvkm_wo32(image, 0x2700, 0xbf800000);
68 	nvkm_wo32(image, 0x3024, 0x000fe000);
69 	nvkm_wo32(image, 0x30a0, 0x000003f8);
70 	nvkm_wo32(image, 0x33fc, 0x002fe000);
71 	for (i = 0x341c; i <= 0x3438; i += 4)
72 		nvkm_wo32(image, i, 0x001c527c);
73 	nvkm_done(image);
74 	return 0;
75 }
76 
77 static struct nvkm_oclass
78 nv2a_gr_cclass = {
79 	.handle = NV_ENGCTX(GR, 0x2a),
80 	.ofuncs = &(struct nvkm_ofuncs) {
81 		.ctor = nv2a_gr_context_ctor,
82 		.dtor = _nvkm_gr_context_dtor,
83 		.init = nv20_gr_context_init,
84 		.fini = nv20_gr_context_fini,
85 		.rd32 = _nvkm_gr_context_rd32,
86 		.wr32 = _nvkm_gr_context_wr32,
87 	},
88 };
89 
90 /*******************************************************************************
91  * PGRAPH engine/subdev functions
92  ******************************************************************************/
93 
94 static int
95 nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
96 	     struct nvkm_oclass *oclass, void *data, u32 size,
97 	     struct nvkm_object **pobject)
98 {
99 	struct nvkm_device *device = (void *)parent;
100 	struct nv20_gr *gr;
101 	int ret;
102 
103 	ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
104 	*pobject = nv_object(gr);
105 	if (ret)
106 		return ret;
107 
108 	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true,
109 			      &gr->ctxtab);
110 	if (ret)
111 		return ret;
112 
113 	nv_subdev(gr)->unit = 0x00001000;
114 	nv_subdev(gr)->intr = nv20_gr_intr;
115 	nv_engine(gr)->cclass = &nv2a_gr_cclass;
116 	nv_engine(gr)->sclass = nv25_gr_sclass;
117 	nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
118 	return 0;
119 }
120 
121 struct nvkm_oclass
122 nv2a_gr_oclass = {
123 	.handle = NV_ENGINE(GR, 0x2a),
124 	.ofuncs = &(struct nvkm_ofuncs) {
125 		.ctor = nv2a_gr_ctor,
126 		.dtor = nv20_gr_dtor,
127 		.init = nv20_gr_init,
128 		.fini = _nvkm_gr_fini,
129 	},
130 };
131