1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <engine/fifo.h> 5 #include <engine/fifo/chan.h> 6 7 /******************************************************************************* 8 * PGRAPH context 9 ******************************************************************************/ 10 11 static const struct nvkm_object_func 12 nv2a_gr_chan = { 13 .dtor = nv20_gr_chan_dtor, 14 .init = nv20_gr_chan_init, 15 .fini = nv20_gr_chan_fini, 16 }; 17 18 static int 19 nv2a_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, 20 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) 21 { 22 struct nv20_gr *gr = nv20_gr(base); 23 struct nv20_gr_chan *chan; 24 int ret, i; 25 26 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 27 return -ENOMEM; 28 nvkm_object_ctor(&nv2a_gr_chan, oclass, &chan->object); 29 chan->gr = gr; 30 chan->chid = fifoch->chid; 31 *pobject = &chan->object; 32 33 ret = nvkm_memory_new(gr->base.engine.subdev.device, 34 NVKM_MEM_TARGET_INST, 0x36b0, 16, true, 35 &chan->inst); 36 if (ret) 37 return ret; 38 39 nvkm_kmap(chan->inst); 40 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); 41 nvkm_wo32(chan->inst, 0x033c, 0xffff0000); 42 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); 43 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); 44 nvkm_wo32(chan->inst, 0x047c, 0x00000101); 45 nvkm_wo32(chan->inst, 0x0490, 0x00000111); 46 nvkm_wo32(chan->inst, 0x04a8, 0x44400000); 47 for (i = 0x04d4; i <= 0x04e0; i += 4) 48 nvkm_wo32(chan->inst, i, 0x00030303); 49 for (i = 0x04f4; i <= 0x0500; i += 4) 50 nvkm_wo32(chan->inst, i, 0x00080000); 51 for (i = 0x050c; i <= 0x0518; i += 4) 52 nvkm_wo32(chan->inst, i, 0x01012000); 53 for (i = 0x051c; i <= 0x0528; i += 4) 54 nvkm_wo32(chan->inst, i, 0x000105b8); 55 for (i = 0x052c; i <= 0x0538; i += 4) 56 nvkm_wo32(chan->inst, i, 0x00080008); 57 for (i = 0x055c; i <= 0x0598; i += 4) 58 nvkm_wo32(chan->inst, i, 0x07ff0000); 59 nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff); 60 nvkm_wo32(chan->inst, 0x05fc, 0x00000001); 61 nvkm_wo32(chan->inst, 0x0604, 0x00004000); 62 nvkm_wo32(chan->inst, 0x0610, 0x00000001); 63 nvkm_wo32(chan->inst, 0x0618, 0x00040000); 64 nvkm_wo32(chan->inst, 0x061c, 0x00010000); 65 for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ 66 nvkm_wo32(chan->inst, (i + 0), 0x10700ff9); 67 nvkm_wo32(chan->inst, (i + 4), 0x0436086c); 68 nvkm_wo32(chan->inst, (i + 8), 0x000c001b); 69 } 70 nvkm_wo32(chan->inst, 0x269c, 0x3f800000); 71 nvkm_wo32(chan->inst, 0x26b0, 0x3f800000); 72 nvkm_wo32(chan->inst, 0x26dc, 0x40000000); 73 nvkm_wo32(chan->inst, 0x26e0, 0x3f800000); 74 nvkm_wo32(chan->inst, 0x26e4, 0x3f000000); 75 nvkm_wo32(chan->inst, 0x26ec, 0x40000000); 76 nvkm_wo32(chan->inst, 0x26f0, 0x3f800000); 77 nvkm_wo32(chan->inst, 0x26f8, 0xbf800000); 78 nvkm_wo32(chan->inst, 0x2700, 0xbf800000); 79 nvkm_wo32(chan->inst, 0x3024, 0x000fe000); 80 nvkm_wo32(chan->inst, 0x30a0, 0x000003f8); 81 nvkm_wo32(chan->inst, 0x33fc, 0x002fe000); 82 for (i = 0x341c; i <= 0x3438; i += 4) 83 nvkm_wo32(chan->inst, i, 0x001c527c); 84 nvkm_done(chan->inst); 85 return 0; 86 } 87 88 /******************************************************************************* 89 * PGRAPH engine/subdev functions 90 ******************************************************************************/ 91 92 static const struct nvkm_gr_func 93 nv2a_gr = { 94 .chan_new = nv2a_gr_chan_new, 95 .sclass = { 96 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ 97 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ 98 { -1, -1, 0x0030, &nv04_gr_object }, /* null */ 99 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ 100 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ 101 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ 102 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ 103 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ 104 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ 105 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ 106 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ 107 { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ 108 { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */ 109 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ 110 { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */ 111 {} 112 } 113 }; 114 115 static int 116 nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 117 struct nvkm_oclass *oclass, void *data, u32 size, 118 struct nvkm_object **pobject) 119 { 120 struct nvkm_device *device = (void *)parent; 121 struct nv20_gr *gr; 122 int ret; 123 124 ret = nvkm_gr_create(parent, engine, oclass, true, &gr); 125 *pobject = nv_object(gr); 126 if (ret) 127 return ret; 128 129 gr->base.func = &nv2a_gr; 130 131 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, 132 &gr->ctxtab); 133 if (ret) 134 return ret; 135 136 nv_subdev(gr)->unit = 0x00001000; 137 nv_subdev(gr)->intr = nv20_gr_intr; 138 nv_engine(gr)->tile_prog = nv20_gr_tile_prog; 139 return 0; 140 } 141 142 struct nvkm_oclass 143 nv2a_gr_oclass = { 144 .handle = NV_ENGINE(GR, 0x2a), 145 .ofuncs = &(struct nvkm_ofuncs) { 146 .ctor = nv2a_gr_ctor, 147 .dtor = nv20_gr_dtor, 148 .init = nv20_gr_init, 149 .fini = _nvkm_gr_fini, 150 }, 151 }; 152