1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <engine/fifo.h> 5 6 /******************************************************************************* 7 * Graphics object classes 8 ******************************************************************************/ 9 10 struct nvkm_oclass 11 nv25_gr_sclass[] = { 12 { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ 13 { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ 14 { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ 15 { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ 16 { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ 17 { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ 18 { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ 19 { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ 20 { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ 21 { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ 22 { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ 23 { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */ 24 { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */ 25 { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ 26 { 0x0597, &nv04_gr_ofuncs, NULL }, /* kelvin */ 27 {}, 28 }; 29 30 /******************************************************************************* 31 * PGRAPH context 32 ******************************************************************************/ 33 34 static int 35 nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 36 struct nvkm_oclass *oclass, void *data, u32 size, 37 struct nvkm_object **pobject) 38 { 39 struct nv20_gr_chan *chan; 40 int ret, i; 41 42 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724, 43 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); 44 *pobject = nv_object(chan); 45 if (ret) 46 return ret; 47 48 chan->chid = nvkm_fifo_chan(parent)->chid; 49 50 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); 51 nv_wo32(chan, 0x035c, 0xffff0000); 52 nv_wo32(chan, 0x03c0, 0x0fff0000); 53 nv_wo32(chan, 0x03c4, 0x0fff0000); 54 nv_wo32(chan, 0x049c, 0x00000101); 55 nv_wo32(chan, 0x04b0, 0x00000111); 56 nv_wo32(chan, 0x04c8, 0x00000080); 57 nv_wo32(chan, 0x04cc, 0xffff0000); 58 nv_wo32(chan, 0x04d0, 0x00000001); 59 nv_wo32(chan, 0x04e4, 0x44400000); 60 nv_wo32(chan, 0x04fc, 0x4b800000); 61 for (i = 0x0510; i <= 0x051c; i += 4) 62 nv_wo32(chan, i, 0x00030303); 63 for (i = 0x0530; i <= 0x053c; i += 4) 64 nv_wo32(chan, i, 0x00080000); 65 for (i = 0x0548; i <= 0x0554; i += 4) 66 nv_wo32(chan, i, 0x01012000); 67 for (i = 0x0558; i <= 0x0564; i += 4) 68 nv_wo32(chan, i, 0x000105b8); 69 for (i = 0x0568; i <= 0x0574; i += 4) 70 nv_wo32(chan, i, 0x00080008); 71 for (i = 0x0598; i <= 0x05d4; i += 4) 72 nv_wo32(chan, i, 0x07ff0000); 73 nv_wo32(chan, 0x05e0, 0x4b7fffff); 74 nv_wo32(chan, 0x0620, 0x00000080); 75 nv_wo32(chan, 0x0624, 0x30201000); 76 nv_wo32(chan, 0x0628, 0x70605040); 77 nv_wo32(chan, 0x062c, 0xb0a09080); 78 nv_wo32(chan, 0x0630, 0xf0e0d0c0); 79 nv_wo32(chan, 0x0664, 0x00000001); 80 nv_wo32(chan, 0x066c, 0x00004000); 81 nv_wo32(chan, 0x0678, 0x00000001); 82 nv_wo32(chan, 0x0680, 0x00040000); 83 nv_wo32(chan, 0x0684, 0x00010000); 84 for (i = 0x1b04; i <= 0x2374; i += 16) { 85 nv_wo32(chan, (i + 0), 0x10700ff9); 86 nv_wo32(chan, (i + 4), 0x0436086c); 87 nv_wo32(chan, (i + 8), 0x000c001b); 88 } 89 nv_wo32(chan, 0x2704, 0x3f800000); 90 nv_wo32(chan, 0x2718, 0x3f800000); 91 nv_wo32(chan, 0x2744, 0x40000000); 92 nv_wo32(chan, 0x2748, 0x3f800000); 93 nv_wo32(chan, 0x274c, 0x3f000000); 94 nv_wo32(chan, 0x2754, 0x40000000); 95 nv_wo32(chan, 0x2758, 0x3f800000); 96 nv_wo32(chan, 0x2760, 0xbf800000); 97 nv_wo32(chan, 0x2768, 0xbf800000); 98 nv_wo32(chan, 0x308c, 0x000fe000); 99 nv_wo32(chan, 0x3108, 0x000003f8); 100 nv_wo32(chan, 0x3468, 0x002fe000); 101 for (i = 0x3484; i <= 0x34a0; i += 4) 102 nv_wo32(chan, i, 0x001c527c); 103 return 0; 104 } 105 106 static struct nvkm_oclass 107 nv25_gr_cclass = { 108 .handle = NV_ENGCTX(GR, 0x25), 109 .ofuncs = &(struct nvkm_ofuncs) { 110 .ctor = nv25_gr_context_ctor, 111 .dtor = _nvkm_gr_context_dtor, 112 .init = nv20_gr_context_init, 113 .fini = nv20_gr_context_fini, 114 .rd32 = _nvkm_gr_context_rd32, 115 .wr32 = _nvkm_gr_context_wr32, 116 }, 117 }; 118 119 /******************************************************************************* 120 * PGRAPH engine/subdev functions 121 ******************************************************************************/ 122 123 static int 124 nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 125 struct nvkm_oclass *oclass, void *data, u32 size, 126 struct nvkm_object **pobject) 127 { 128 struct nv20_gr_priv *priv; 129 int ret; 130 131 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); 132 *pobject = nv_object(priv); 133 if (ret) 134 return ret; 135 136 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, 137 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); 138 if (ret) 139 return ret; 140 141 nv_subdev(priv)->unit = 0x00001000; 142 nv_subdev(priv)->intr = nv20_gr_intr; 143 nv_engine(priv)->cclass = &nv25_gr_cclass; 144 nv_engine(priv)->sclass = nv25_gr_sclass; 145 nv_engine(priv)->tile_prog = nv20_gr_tile_prog; 146 return 0; 147 } 148 149 struct nvkm_oclass 150 nv25_gr_oclass = { 151 .handle = NV_ENGINE(GR, 0x25), 152 .ofuncs = &(struct nvkm_ofuncs) { 153 .ctor = nv25_gr_ctor, 154 .dtor = nv20_gr_dtor, 155 .init = nv20_gr_init, 156 .fini = _nvkm_gr_fini, 157 }, 158 }; 159