1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <engine/fifo.h> 5 6 /******************************************************************************* 7 * Graphics object classes 8 ******************************************************************************/ 9 10 struct nvkm_oclass 11 nv25_gr_sclass[] = { 12 { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ 13 { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ 14 { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ 15 { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ 16 { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ 17 { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ 18 { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ 19 { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ 20 { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ 21 { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ 22 { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ 23 { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */ 24 { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */ 25 { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ 26 { 0x0597, &nv04_gr_ofuncs, NULL }, /* kelvin */ 27 {}, 28 }; 29 30 /******************************************************************************* 31 * PGRAPH context 32 ******************************************************************************/ 33 34 static int 35 nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 36 struct nvkm_oclass *oclass, void *data, u32 size, 37 struct nvkm_object **pobject) 38 { 39 struct nv20_gr_chan *chan; 40 struct nvkm_gpuobj *image; 41 int ret, i; 42 43 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724, 44 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); 45 *pobject = nv_object(chan); 46 if (ret) 47 return ret; 48 49 chan->chid = nvkm_fifo_chan(parent)->chid; 50 image = &chan->base.base.gpuobj; 51 52 nvkm_kmap(image); 53 nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); 54 nvkm_wo32(image, 0x035c, 0xffff0000); 55 nvkm_wo32(image, 0x03c0, 0x0fff0000); 56 nvkm_wo32(image, 0x03c4, 0x0fff0000); 57 nvkm_wo32(image, 0x049c, 0x00000101); 58 nvkm_wo32(image, 0x04b0, 0x00000111); 59 nvkm_wo32(image, 0x04c8, 0x00000080); 60 nvkm_wo32(image, 0x04cc, 0xffff0000); 61 nvkm_wo32(image, 0x04d0, 0x00000001); 62 nvkm_wo32(image, 0x04e4, 0x44400000); 63 nvkm_wo32(image, 0x04fc, 0x4b800000); 64 for (i = 0x0510; i <= 0x051c; i += 4) 65 nvkm_wo32(image, i, 0x00030303); 66 for (i = 0x0530; i <= 0x053c; i += 4) 67 nvkm_wo32(image, i, 0x00080000); 68 for (i = 0x0548; i <= 0x0554; i += 4) 69 nvkm_wo32(image, i, 0x01012000); 70 for (i = 0x0558; i <= 0x0564; i += 4) 71 nvkm_wo32(image, i, 0x000105b8); 72 for (i = 0x0568; i <= 0x0574; i += 4) 73 nvkm_wo32(image, i, 0x00080008); 74 for (i = 0x0598; i <= 0x05d4; i += 4) 75 nvkm_wo32(image, i, 0x07ff0000); 76 nvkm_wo32(image, 0x05e0, 0x4b7fffff); 77 nvkm_wo32(image, 0x0620, 0x00000080); 78 nvkm_wo32(image, 0x0624, 0x30201000); 79 nvkm_wo32(image, 0x0628, 0x70605040); 80 nvkm_wo32(image, 0x062c, 0xb0a09080); 81 nvkm_wo32(image, 0x0630, 0xf0e0d0c0); 82 nvkm_wo32(image, 0x0664, 0x00000001); 83 nvkm_wo32(image, 0x066c, 0x00004000); 84 nvkm_wo32(image, 0x0678, 0x00000001); 85 nvkm_wo32(image, 0x0680, 0x00040000); 86 nvkm_wo32(image, 0x0684, 0x00010000); 87 for (i = 0x1b04; i <= 0x2374; i += 16) { 88 nvkm_wo32(image, (i + 0), 0x10700ff9); 89 nvkm_wo32(image, (i + 4), 0x0436086c); 90 nvkm_wo32(image, (i + 8), 0x000c001b); 91 } 92 nvkm_wo32(image, 0x2704, 0x3f800000); 93 nvkm_wo32(image, 0x2718, 0x3f800000); 94 nvkm_wo32(image, 0x2744, 0x40000000); 95 nvkm_wo32(image, 0x2748, 0x3f800000); 96 nvkm_wo32(image, 0x274c, 0x3f000000); 97 nvkm_wo32(image, 0x2754, 0x40000000); 98 nvkm_wo32(image, 0x2758, 0x3f800000); 99 nvkm_wo32(image, 0x2760, 0xbf800000); 100 nvkm_wo32(image, 0x2768, 0xbf800000); 101 nvkm_wo32(image, 0x308c, 0x000fe000); 102 nvkm_wo32(image, 0x3108, 0x000003f8); 103 nvkm_wo32(image, 0x3468, 0x002fe000); 104 for (i = 0x3484; i <= 0x34a0; i += 4) 105 nvkm_wo32(image, i, 0x001c527c); 106 nvkm_done(image); 107 return 0; 108 } 109 110 static struct nvkm_oclass 111 nv25_gr_cclass = { 112 .handle = NV_ENGCTX(GR, 0x25), 113 .ofuncs = &(struct nvkm_ofuncs) { 114 .ctor = nv25_gr_context_ctor, 115 .dtor = _nvkm_gr_context_dtor, 116 .init = nv20_gr_context_init, 117 .fini = nv20_gr_context_fini, 118 .rd32 = _nvkm_gr_context_rd32, 119 .wr32 = _nvkm_gr_context_wr32, 120 }, 121 }; 122 123 /******************************************************************************* 124 * PGRAPH engine/subdev functions 125 ******************************************************************************/ 126 127 static int 128 nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 129 struct nvkm_oclass *oclass, void *data, u32 size, 130 struct nvkm_object **pobject) 131 { 132 struct nvkm_device *device = (void *)parent; 133 struct nv20_gr *gr; 134 int ret; 135 136 ret = nvkm_gr_create(parent, engine, oclass, true, &gr); 137 *pobject = nv_object(gr); 138 if (ret) 139 return ret; 140 141 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, 142 &gr->ctxtab); 143 if (ret) 144 return ret; 145 146 nv_subdev(gr)->unit = 0x00001000; 147 nv_subdev(gr)->intr = nv20_gr_intr; 148 nv_engine(gr)->cclass = &nv25_gr_cclass; 149 nv_engine(gr)->sclass = nv25_gr_sclass; 150 nv_engine(gr)->tile_prog = nv20_gr_tile_prog; 151 return 0; 152 } 153 154 struct nvkm_oclass 155 nv25_gr_oclass = { 156 .handle = NV_ENGINE(GR, 0x25), 157 .ofuncs = &(struct nvkm_ofuncs) { 158 .ctor = nv25_gr_ctor, 159 .dtor = nv20_gr_dtor, 160 .init = nv20_gr_init, 161 .fini = _nvkm_gr_fini, 162 }, 163 }; 164