1 // SPDX-License-Identifier: MIT 2 #include "nv20.h" 3 #include "regs.h" 4 5 #include <core/gpuobj.h> 6 #include <engine/fifo.h> 7 #include <engine/fifo/chan.h> 8 9 /******************************************************************************* 10 * PGRAPH context 11 ******************************************************************************/ 12 13 static const struct nvkm_object_func 14 nv25_gr_chan = { 15 .dtor = nv20_gr_chan_dtor, 16 .init = nv20_gr_chan_init, 17 .fini = nv20_gr_chan_fini, 18 }; 19 20 static int 21 nv25_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, 22 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) 23 { 24 struct nv20_gr *gr = nv20_gr(base); 25 struct nv20_gr_chan *chan; 26 int ret, i; 27 28 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 29 return -ENOMEM; 30 nvkm_object_ctor(&nv25_gr_chan, oclass, &chan->object); 31 chan->gr = gr; 32 chan->chid = fifoch->id; 33 *pobject = &chan->object; 34 35 ret = nvkm_memory_new(gr->base.engine.subdev.device, 36 NVKM_MEM_TARGET_INST, 0x3724, 16, true, 37 &chan->inst); 38 if (ret) 39 return ret; 40 41 nvkm_kmap(chan->inst); 42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); 43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); 44 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000); 45 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000); 46 nvkm_wo32(chan->inst, 0x049c, 0x00000101); 47 nvkm_wo32(chan->inst, 0x04b0, 0x00000111); 48 nvkm_wo32(chan->inst, 0x04c8, 0x00000080); 49 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000); 50 nvkm_wo32(chan->inst, 0x04d0, 0x00000001); 51 nvkm_wo32(chan->inst, 0x04e4, 0x44400000); 52 nvkm_wo32(chan->inst, 0x04fc, 0x4b800000); 53 for (i = 0x0510; i <= 0x051c; i += 4) 54 nvkm_wo32(chan->inst, i, 0x00030303); 55 for (i = 0x0530; i <= 0x053c; i += 4) 56 nvkm_wo32(chan->inst, i, 0x00080000); 57 for (i = 0x0548; i <= 0x0554; i += 4) 58 nvkm_wo32(chan->inst, i, 0x01012000); 59 for (i = 0x0558; i <= 0x0564; i += 4) 60 nvkm_wo32(chan->inst, i, 0x000105b8); 61 for (i = 0x0568; i <= 0x0574; i += 4) 62 nvkm_wo32(chan->inst, i, 0x00080008); 63 for (i = 0x0598; i <= 0x05d4; i += 4) 64 nvkm_wo32(chan->inst, i, 0x07ff0000); 65 nvkm_wo32(chan->inst, 0x05e0, 0x4b7fffff); 66 nvkm_wo32(chan->inst, 0x0620, 0x00000080); 67 nvkm_wo32(chan->inst, 0x0624, 0x30201000); 68 nvkm_wo32(chan->inst, 0x0628, 0x70605040); 69 nvkm_wo32(chan->inst, 0x062c, 0xb0a09080); 70 nvkm_wo32(chan->inst, 0x0630, 0xf0e0d0c0); 71 nvkm_wo32(chan->inst, 0x0664, 0x00000001); 72 nvkm_wo32(chan->inst, 0x066c, 0x00004000); 73 nvkm_wo32(chan->inst, 0x0678, 0x00000001); 74 nvkm_wo32(chan->inst, 0x0680, 0x00040000); 75 nvkm_wo32(chan->inst, 0x0684, 0x00010000); 76 for (i = 0x1b04; i <= 0x2374; i += 16) { 77 nvkm_wo32(chan->inst, (i + 0), 0x10700ff9); 78 nvkm_wo32(chan->inst, (i + 4), 0x0436086c); 79 nvkm_wo32(chan->inst, (i + 8), 0x000c001b); 80 } 81 nvkm_wo32(chan->inst, 0x2704, 0x3f800000); 82 nvkm_wo32(chan->inst, 0x2718, 0x3f800000); 83 nvkm_wo32(chan->inst, 0x2744, 0x40000000); 84 nvkm_wo32(chan->inst, 0x2748, 0x3f800000); 85 nvkm_wo32(chan->inst, 0x274c, 0x3f000000); 86 nvkm_wo32(chan->inst, 0x2754, 0x40000000); 87 nvkm_wo32(chan->inst, 0x2758, 0x3f800000); 88 nvkm_wo32(chan->inst, 0x2760, 0xbf800000); 89 nvkm_wo32(chan->inst, 0x2768, 0xbf800000); 90 nvkm_wo32(chan->inst, 0x308c, 0x000fe000); 91 nvkm_wo32(chan->inst, 0x3108, 0x000003f8); 92 nvkm_wo32(chan->inst, 0x3468, 0x002fe000); 93 for (i = 0x3484; i <= 0x34a0; i += 4) 94 nvkm_wo32(chan->inst, i, 0x001c527c); 95 nvkm_done(chan->inst); 96 return 0; 97 } 98 99 /******************************************************************************* 100 * PGRAPH engine/subdev functions 101 ******************************************************************************/ 102 103 static const struct nvkm_gr_func 104 nv25_gr = { 105 .dtor = nv20_gr_dtor, 106 .oneinit = nv20_gr_oneinit, 107 .init = nv20_gr_init, 108 .intr = nv20_gr_intr, 109 .tile = nv20_gr_tile, 110 .chan_new = nv25_gr_chan_new, 111 .sclass = { 112 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ 113 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ 114 { -1, -1, 0x0030, &nv04_gr_object }, /* null */ 115 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ 116 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ 117 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ 118 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ 119 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ 120 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ 121 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ 122 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ 123 { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ 124 { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */ 125 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ 126 { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */ 127 {} 128 } 129 }; 130 131 int 132 nv25_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) 133 { 134 return nv20_gr_new_(&nv25_gr, device, type, inst, pgr); 135 } 136