1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <core/client.h> 5 #include <core/handle.h> 6 #include <engine/fifo.h> 7 #include <subdev/fb.h> 8 #include <subdev/timer.h> 9 10 /******************************************************************************* 11 * Graphics object classes 12 ******************************************************************************/ 13 14 static struct nvkm_oclass 15 nv20_gr_sclass[] = { 16 { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ 17 { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ 18 { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ 19 { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ 20 { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ 21 { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ 22 { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ 23 { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ 24 { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ 25 { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ 26 { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ 27 { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */ 28 { 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */ 29 { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */ 30 { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ 31 {}, 32 }; 33 34 /******************************************************************************* 35 * PGRAPH context 36 ******************************************************************************/ 37 38 static int 39 nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 40 struct nvkm_oclass *oclass, void *data, u32 size, 41 struct nvkm_object **pobject) 42 { 43 struct nv20_gr_chan *chan; 44 int ret, i; 45 46 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0, 47 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); 48 *pobject = nv_object(chan); 49 if (ret) 50 return ret; 51 52 chan->chid = nvkm_fifo_chan(parent)->chid; 53 54 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); 55 nv_wo32(chan, 0x033c, 0xffff0000); 56 nv_wo32(chan, 0x03a0, 0x0fff0000); 57 nv_wo32(chan, 0x03a4, 0x0fff0000); 58 nv_wo32(chan, 0x047c, 0x00000101); 59 nv_wo32(chan, 0x0490, 0x00000111); 60 nv_wo32(chan, 0x04a8, 0x44400000); 61 for (i = 0x04d4; i <= 0x04e0; i += 4) 62 nv_wo32(chan, i, 0x00030303); 63 for (i = 0x04f4; i <= 0x0500; i += 4) 64 nv_wo32(chan, i, 0x00080000); 65 for (i = 0x050c; i <= 0x0518; i += 4) 66 nv_wo32(chan, i, 0x01012000); 67 for (i = 0x051c; i <= 0x0528; i += 4) 68 nv_wo32(chan, i, 0x000105b8); 69 for (i = 0x052c; i <= 0x0538; i += 4) 70 nv_wo32(chan, i, 0x00080008); 71 for (i = 0x055c; i <= 0x0598; i += 4) 72 nv_wo32(chan, i, 0x07ff0000); 73 nv_wo32(chan, 0x05a4, 0x4b7fffff); 74 nv_wo32(chan, 0x05fc, 0x00000001); 75 nv_wo32(chan, 0x0604, 0x00004000); 76 nv_wo32(chan, 0x0610, 0x00000001); 77 nv_wo32(chan, 0x0618, 0x00040000); 78 nv_wo32(chan, 0x061c, 0x00010000); 79 for (i = 0x1c1c; i <= 0x248c; i += 16) { 80 nv_wo32(chan, (i + 0), 0x10700ff9); 81 nv_wo32(chan, (i + 4), 0x0436086c); 82 nv_wo32(chan, (i + 8), 0x000c001b); 83 } 84 nv_wo32(chan, 0x281c, 0x3f800000); 85 nv_wo32(chan, 0x2830, 0x3f800000); 86 nv_wo32(chan, 0x285c, 0x40000000); 87 nv_wo32(chan, 0x2860, 0x3f800000); 88 nv_wo32(chan, 0x2864, 0x3f000000); 89 nv_wo32(chan, 0x286c, 0x40000000); 90 nv_wo32(chan, 0x2870, 0x3f800000); 91 nv_wo32(chan, 0x2878, 0xbf800000); 92 nv_wo32(chan, 0x2880, 0xbf800000); 93 nv_wo32(chan, 0x34a4, 0x000fe000); 94 nv_wo32(chan, 0x3530, 0x000003f8); 95 nv_wo32(chan, 0x3540, 0x002fe000); 96 for (i = 0x355c; i <= 0x3578; i += 4) 97 nv_wo32(chan, i, 0x001c527c); 98 return 0; 99 } 100 101 int 102 nv20_gr_context_init(struct nvkm_object *object) 103 { 104 struct nv20_gr_priv *priv = (void *)object->engine; 105 struct nv20_gr_chan *chan = (void *)object; 106 int ret; 107 108 ret = nvkm_gr_context_init(&chan->base); 109 if (ret) 110 return ret; 111 112 nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); 113 return 0; 114 } 115 116 int 117 nv20_gr_context_fini(struct nvkm_object *object, bool suspend) 118 { 119 struct nv20_gr_priv *priv = (void *)object->engine; 120 struct nv20_gr_chan *chan = (void *)object; 121 int chid = -1; 122 123 nv_mask(priv, 0x400720, 0x00000001, 0x00000000); 124 if (nv_rd32(priv, 0x400144) & 0x00010000) 125 chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24; 126 if (chan->chid == chid) { 127 nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4); 128 nv_wr32(priv, 0x400788, 0x00000002); 129 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); 130 nv_wr32(priv, 0x400144, 0x10000000); 131 nv_mask(priv, 0x400148, 0xff000000, 0x1f000000); 132 } 133 nv_mask(priv, 0x400720, 0x00000001, 0x00000001); 134 135 nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000); 136 return nvkm_gr_context_fini(&chan->base, suspend); 137 } 138 139 static struct nvkm_oclass 140 nv20_gr_cclass = { 141 .handle = NV_ENGCTX(GR, 0x20), 142 .ofuncs = &(struct nvkm_ofuncs) { 143 .ctor = nv20_gr_context_ctor, 144 .dtor = _nvkm_gr_context_dtor, 145 .init = nv20_gr_context_init, 146 .fini = nv20_gr_context_fini, 147 .rd32 = _nvkm_gr_context_rd32, 148 .wr32 = _nvkm_gr_context_wr32, 149 }, 150 }; 151 152 /******************************************************************************* 153 * PGRAPH engine/subdev functions 154 ******************************************************************************/ 155 156 void 157 nv20_gr_tile_prog(struct nvkm_engine *engine, int i) 158 { 159 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; 160 struct nvkm_fifo *pfifo = nvkm_fifo(engine); 161 struct nv20_gr_priv *priv = (void *)engine; 162 unsigned long flags; 163 164 pfifo->pause(pfifo, &flags); 165 nv04_gr_idle(priv); 166 167 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); 168 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); 169 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); 170 171 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); 172 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit); 173 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); 174 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch); 175 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); 176 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr); 177 178 if (nv_device(engine)->chipset != 0x34) { 179 nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); 180 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); 181 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp); 182 } 183 184 pfifo->start(pfifo, &flags); 185 } 186 187 void 188 nv20_gr_intr(struct nvkm_subdev *subdev) 189 { 190 struct nvkm_engine *engine = nv_engine(subdev); 191 struct nvkm_object *engctx; 192 struct nvkm_handle *handle; 193 struct nv20_gr_priv *priv = (void *)subdev; 194 u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); 195 u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); 196 u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); 197 u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); 198 u32 chid = (addr & 0x01f00000) >> 20; 199 u32 subc = (addr & 0x00070000) >> 16; 200 u32 mthd = (addr & 0x00001ffc); 201 u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); 202 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; 203 u32 show = stat; 204 205 engctx = nvkm_engctx_get(engine, chid); 206 if (stat & NV_PGRAPH_INTR_ERROR) { 207 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { 208 handle = nvkm_handle_get_class(engctx, class); 209 if (handle && !nv_call(handle->object, mthd, data)) 210 show &= ~NV_PGRAPH_INTR_ERROR; 211 nvkm_handle_put(handle); 212 } 213 } 214 215 nv_wr32(priv, NV03_PGRAPH_INTR, stat); 216 nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); 217 218 if (show) { 219 nv_error(priv, "%s", ""); 220 nvkm_bitfield_print(nv10_gr_intr_name, show); 221 pr_cont(" nsource:"); 222 nvkm_bitfield_print(nv04_gr_nsource, nsource); 223 pr_cont(" nstatus:"); 224 nvkm_bitfield_print(nv10_gr_nstatus, nstatus); 225 pr_cont("\n"); 226 nv_error(priv, 227 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 228 chid, nvkm_client_name(engctx), subc, class, mthd, 229 data); 230 } 231 232 nvkm_engctx_put(engctx); 233 } 234 235 static int 236 nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 237 struct nvkm_oclass *oclass, void *data, u32 size, 238 struct nvkm_object **pobject) 239 { 240 struct nv20_gr_priv *priv; 241 int ret; 242 243 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); 244 *pobject = nv_object(priv); 245 if (ret) 246 return ret; 247 248 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, 249 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); 250 if (ret) 251 return ret; 252 253 nv_subdev(priv)->unit = 0x00001000; 254 nv_subdev(priv)->intr = nv20_gr_intr; 255 nv_engine(priv)->cclass = &nv20_gr_cclass; 256 nv_engine(priv)->sclass = nv20_gr_sclass; 257 nv_engine(priv)->tile_prog = nv20_gr_tile_prog; 258 return 0; 259 } 260 261 void 262 nv20_gr_dtor(struct nvkm_object *object) 263 { 264 struct nv20_gr_priv *priv = (void *)object; 265 nvkm_gpuobj_ref(NULL, &priv->ctxtab); 266 nvkm_gr_destroy(&priv->base); 267 } 268 269 int 270 nv20_gr_init(struct nvkm_object *object) 271 { 272 struct nvkm_engine *engine = nv_engine(object); 273 struct nv20_gr_priv *priv = (void *)engine; 274 struct nvkm_fb *fb = nvkm_fb(object); 275 u32 tmp, vramsz; 276 int ret, i; 277 278 ret = nvkm_gr_init(&priv->base); 279 if (ret) 280 return ret; 281 282 nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); 283 284 if (nv_device(priv)->chipset == 0x20) { 285 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000); 286 for (i = 0; i < 15; i++) 287 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); 288 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); 289 } else { 290 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000); 291 for (i = 0; i < 32; i++) 292 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); 293 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); 294 } 295 296 nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); 297 nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 298 299 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); 300 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); 301 nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700); 302 nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ 303 nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000); 304 nv_wr32(priv, 0x40009C , 0x00000040); 305 306 if (nv_device(priv)->chipset >= 0x25) { 307 nv_wr32(priv, 0x400890, 0x00a8cfff); 308 nv_wr32(priv, 0x400610, 0x304B1FB6); 309 nv_wr32(priv, 0x400B80, 0x1cbd3883); 310 nv_wr32(priv, 0x400B84, 0x44000000); 311 nv_wr32(priv, 0x400098, 0x40000080); 312 nv_wr32(priv, 0x400B88, 0x000000ff); 313 314 } else { 315 nv_wr32(priv, 0x400880, 0x0008c7df); 316 nv_wr32(priv, 0x400094, 0x00000005); 317 nv_wr32(priv, 0x400B80, 0x45eae20e); 318 nv_wr32(priv, 0x400B84, 0x24000000); 319 nv_wr32(priv, 0x400098, 0x00000040); 320 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038); 321 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); 322 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038); 323 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); 324 } 325 326 /* Turn all the tiling regions off. */ 327 for (i = 0; i < fb->tile.regions; i++) 328 engine->tile_prog(engine, i); 329 330 nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324)); 331 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); 332 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324)); 333 334 nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 335 nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); 336 337 tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00; 338 nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); 339 tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100; 340 nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); 341 342 /* begin RAM config */ 343 vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; 344 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); 345 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); 346 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); 347 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200)); 348 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); 349 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204)); 350 nv_wr32(priv, 0x400820, 0); 351 nv_wr32(priv, 0x400824, 0); 352 nv_wr32(priv, 0x400864, vramsz - 1); 353 nv_wr32(priv, 0x400868, vramsz - 1); 354 355 /* interesting.. the below overwrites some of the tile setup above.. */ 356 nv_wr32(priv, 0x400B20, 0x00000000); 357 nv_wr32(priv, 0x400B04, 0xFFFFFFFF); 358 359 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); 360 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); 361 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); 362 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); 363 return 0; 364 } 365 366 struct nvkm_oclass 367 nv20_gr_oclass = { 368 .handle = NV_ENGINE(GR, 0x20), 369 .ofuncs = &(struct nvkm_ofuncs) { 370 .ctor = nv20_gr_ctor, 371 .dtor = nv20_gr_dtor, 372 .init = nv20_gr_init, 373 .fini = _nvkm_gr_fini, 374 }, 375 }; 376