1 #include "nv20.h"
2 #include "regs.h"
3 
4 #include <core/client.h>
5 #include <core/handle.h>
6 #include <engine/fifo.h>
7 #include <subdev/fb.h>
8 #include <subdev/timer.h>
9 
10 /*******************************************************************************
11  * Graphics object classes
12  ******************************************************************************/
13 
14 static struct nvkm_oclass
15 nv20_gr_sclass[] = {
16 	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
17 	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
18 	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
19 	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
20 	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
21 	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
22 	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
23 	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
24 	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
25 	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
26 	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
27 	{ 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
28 	{ 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */
29 	{ 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
30 	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
31 	{},
32 };
33 
34 /*******************************************************************************
35  * PGRAPH context
36  ******************************************************************************/
37 
38 static int
39 nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
40 		     struct nvkm_oclass *oclass, void *data, u32 size,
41 		     struct nvkm_object **pobject)
42 {
43 	struct nv20_gr_chan *chan;
44 	int ret, i;
45 
46 	ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0,
47 				     16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
48 	*pobject = nv_object(chan);
49 	if (ret)
50 		return ret;
51 
52 	chan->chid = nvkm_fifo_chan(parent)->chid;
53 
54 	nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
55 	nv_wo32(chan, 0x033c, 0xffff0000);
56 	nv_wo32(chan, 0x03a0, 0x0fff0000);
57 	nv_wo32(chan, 0x03a4, 0x0fff0000);
58 	nv_wo32(chan, 0x047c, 0x00000101);
59 	nv_wo32(chan, 0x0490, 0x00000111);
60 	nv_wo32(chan, 0x04a8, 0x44400000);
61 	for (i = 0x04d4; i <= 0x04e0; i += 4)
62 		nv_wo32(chan, i, 0x00030303);
63 	for (i = 0x04f4; i <= 0x0500; i += 4)
64 		nv_wo32(chan, i, 0x00080000);
65 	for (i = 0x050c; i <= 0x0518; i += 4)
66 		nv_wo32(chan, i, 0x01012000);
67 	for (i = 0x051c; i <= 0x0528; i += 4)
68 		nv_wo32(chan, i, 0x000105b8);
69 	for (i = 0x052c; i <= 0x0538; i += 4)
70 		nv_wo32(chan, i, 0x00080008);
71 	for (i = 0x055c; i <= 0x0598; i += 4)
72 		nv_wo32(chan, i, 0x07ff0000);
73 	nv_wo32(chan, 0x05a4, 0x4b7fffff);
74 	nv_wo32(chan, 0x05fc, 0x00000001);
75 	nv_wo32(chan, 0x0604, 0x00004000);
76 	nv_wo32(chan, 0x0610, 0x00000001);
77 	nv_wo32(chan, 0x0618, 0x00040000);
78 	nv_wo32(chan, 0x061c, 0x00010000);
79 	for (i = 0x1c1c; i <= 0x248c; i += 16) {
80 		nv_wo32(chan, (i + 0), 0x10700ff9);
81 		nv_wo32(chan, (i + 4), 0x0436086c);
82 		nv_wo32(chan, (i + 8), 0x000c001b);
83 	}
84 	nv_wo32(chan, 0x281c, 0x3f800000);
85 	nv_wo32(chan, 0x2830, 0x3f800000);
86 	nv_wo32(chan, 0x285c, 0x40000000);
87 	nv_wo32(chan, 0x2860, 0x3f800000);
88 	nv_wo32(chan, 0x2864, 0x3f000000);
89 	nv_wo32(chan, 0x286c, 0x40000000);
90 	nv_wo32(chan, 0x2870, 0x3f800000);
91 	nv_wo32(chan, 0x2878, 0xbf800000);
92 	nv_wo32(chan, 0x2880, 0xbf800000);
93 	nv_wo32(chan, 0x34a4, 0x000fe000);
94 	nv_wo32(chan, 0x3530, 0x000003f8);
95 	nv_wo32(chan, 0x3540, 0x002fe000);
96 	for (i = 0x355c; i <= 0x3578; i += 4)
97 		nv_wo32(chan, i, 0x001c527c);
98 	return 0;
99 }
100 
101 int
102 nv20_gr_context_init(struct nvkm_object *object)
103 {
104 	struct nv20_gr *gr = (void *)object->engine;
105 	struct nv20_gr_chan *chan = (void *)object;
106 	int ret;
107 
108 	ret = nvkm_gr_context_init(&chan->base);
109 	if (ret)
110 		return ret;
111 
112 	nv_wo32(gr->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
113 	return 0;
114 }
115 
116 int
117 nv20_gr_context_fini(struct nvkm_object *object, bool suspend)
118 {
119 	struct nv20_gr *gr = (void *)object->engine;
120 	struct nv20_gr_chan *chan = (void *)object;
121 	struct nvkm_device *device = gr->base.engine.subdev.device;
122 	int chid = -1;
123 
124 	nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
125 	if (nvkm_rd32(device, 0x400144) & 0x00010000)
126 		chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
127 	if (chan->chid == chid) {
128 		nvkm_wr32(device, 0x400784, nv_gpuobj(chan)->addr >> 4);
129 		nvkm_wr32(device, 0x400788, 0x00000002);
130 		nvkm_msec(device, 2000,
131 			if (!nvkm_rd32(device, 0x400700))
132 				break;
133 		);
134 		nvkm_wr32(device, 0x400144, 0x10000000);
135 		nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
136 	}
137 	nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
138 
139 	nv_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
140 	return nvkm_gr_context_fini(&chan->base, suspend);
141 }
142 
143 static struct nvkm_oclass
144 nv20_gr_cclass = {
145 	.handle = NV_ENGCTX(GR, 0x20),
146 	.ofuncs = &(struct nvkm_ofuncs) {
147 		.ctor = nv20_gr_context_ctor,
148 		.dtor = _nvkm_gr_context_dtor,
149 		.init = nv20_gr_context_init,
150 		.fini = nv20_gr_context_fini,
151 		.rd32 = _nvkm_gr_context_rd32,
152 		.wr32 = _nvkm_gr_context_wr32,
153 	},
154 };
155 
156 /*******************************************************************************
157  * PGRAPH engine/subdev functions
158  ******************************************************************************/
159 
160 void
161 nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
162 {
163 	struct nv20_gr *gr = (void *)engine;
164 	struct nvkm_device *device = gr->base.engine.subdev.device;
165 	struct nvkm_fifo *fifo = device->fifo;
166 	struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
167 	unsigned long flags;
168 
169 	fifo->pause(fifo, &flags);
170 	nv04_gr_idle(gr);
171 
172 	nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
173 	nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
174 	nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
175 
176 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
177 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
178 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
179 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
180 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
181 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
182 
183 	if (nv_device(engine)->chipset != 0x34) {
184 		nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
185 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
186 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
187 	}
188 
189 	fifo->start(fifo, &flags);
190 }
191 
192 void
193 nv20_gr_intr(struct nvkm_subdev *subdev)
194 {
195 	struct nvkm_engine *engine = nv_engine(subdev);
196 	struct nvkm_object *engctx;
197 	struct nvkm_handle *handle;
198 	struct nv20_gr *gr = (void *)subdev;
199 	struct nvkm_device *device = gr->base.engine.subdev.device;
200 	u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
201 	u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
202 	u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
203 	u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
204 	u32 chid = (addr & 0x01f00000) >> 20;
205 	u32 subc = (addr & 0x00070000) >> 16;
206 	u32 mthd = (addr & 0x00001ffc);
207 	u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
208 	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
209 	u32 show = stat;
210 	char msg[128], src[128], sta[128];
211 
212 	engctx = nvkm_engctx_get(engine, chid);
213 	if (stat & NV_PGRAPH_INTR_ERROR) {
214 		if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
215 			handle = nvkm_handle_get_class(engctx, class);
216 			if (handle && !nv_call(handle->object, mthd, data))
217 				show &= ~NV_PGRAPH_INTR_ERROR;
218 			nvkm_handle_put(handle);
219 		}
220 	}
221 
222 	nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
223 	nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
224 
225 	if (show) {
226 		nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
227 		nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
228 		nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
229 		nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
230 				   "nstatus %08x [%s] ch %d [%s] subc %d "
231 				   "class %04x mthd %04x data %08x\n",
232 			   show, msg, nsource, src, nstatus, sta, chid,
233 			   nvkm_client_name(engctx), subc, class, mthd, data);
234 	}
235 
236 	nvkm_engctx_put(engctx);
237 }
238 
239 static int
240 nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
241 	     struct nvkm_oclass *oclass, void *data, u32 size,
242 	     struct nvkm_object **pobject)
243 {
244 	struct nv20_gr *gr;
245 	int ret;
246 
247 	ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
248 	*pobject = nv_object(gr);
249 	if (ret)
250 		return ret;
251 
252 	ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16,
253 			      NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab);
254 	if (ret)
255 		return ret;
256 
257 	nv_subdev(gr)->unit = 0x00001000;
258 	nv_subdev(gr)->intr = nv20_gr_intr;
259 	nv_engine(gr)->cclass = &nv20_gr_cclass;
260 	nv_engine(gr)->sclass = nv20_gr_sclass;
261 	nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
262 	return 0;
263 }
264 
265 void
266 nv20_gr_dtor(struct nvkm_object *object)
267 {
268 	struct nv20_gr *gr = (void *)object;
269 	nvkm_gpuobj_ref(NULL, &gr->ctxtab);
270 	nvkm_gr_destroy(&gr->base);
271 }
272 
273 int
274 nv20_gr_init(struct nvkm_object *object)
275 {
276 	struct nvkm_engine *engine = nv_engine(object);
277 	struct nv20_gr *gr = (void *)engine;
278 	struct nvkm_device *device = gr->base.engine.subdev.device;
279 	struct nvkm_fb *fb = device->fb;
280 	u32 tmp, vramsz;
281 	int ret, i;
282 
283 	ret = nvkm_gr_init(&gr->base);
284 	if (ret)
285 		return ret;
286 
287 	nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4);
288 
289 	if (nv_device(gr)->chipset == 0x20) {
290 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
291 		for (i = 0; i < 15; i++)
292 			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
293 		nvkm_msec(device, 2000,
294 			if (!nvkm_rd32(device, 0x400700))
295 				break;
296 		);
297 	} else {
298 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
299 		for (i = 0; i < 32; i++)
300 			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
301 		nvkm_msec(device, 2000,
302 			if (!nvkm_rd32(device, 0x400700))
303 				break;
304 		);
305 	}
306 
307 	nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
308 	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
309 
310 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
311 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
312 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
313 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
314 	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
315 	nvkm_wr32(device, 0x40009C           , 0x00000040);
316 
317 	if (nv_device(gr)->chipset >= 0x25) {
318 		nvkm_wr32(device, 0x400890, 0x00a8cfff);
319 		nvkm_wr32(device, 0x400610, 0x304B1FB6);
320 		nvkm_wr32(device, 0x400B80, 0x1cbd3883);
321 		nvkm_wr32(device, 0x400B84, 0x44000000);
322 		nvkm_wr32(device, 0x400098, 0x40000080);
323 		nvkm_wr32(device, 0x400B88, 0x000000ff);
324 
325 	} else {
326 		nvkm_wr32(device, 0x400880, 0x0008c7df);
327 		nvkm_wr32(device, 0x400094, 0x00000005);
328 		nvkm_wr32(device, 0x400B80, 0x45eae20e);
329 		nvkm_wr32(device, 0x400B84, 0x24000000);
330 		nvkm_wr32(device, 0x400098, 0x00000040);
331 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
332 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
333 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
334 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
335 	}
336 
337 	/* Turn all the tiling regions off. */
338 	for (i = 0; i < fb->tile.regions; i++)
339 		engine->tile_prog(engine, i);
340 
341 	nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
342 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
343 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));
344 
345 	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
346 	nvkm_wr32(device, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
347 
348 	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
349 	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
350 	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;
351 	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
352 
353 	/* begin RAM config */
354 	vramsz = nv_device_resource_len(nv_device(gr), 1) - 1;
355 	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
356 	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
357 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
358 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
359 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
360 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
361 	nvkm_wr32(device, 0x400820, 0);
362 	nvkm_wr32(device, 0x400824, 0);
363 	nvkm_wr32(device, 0x400864, vramsz - 1);
364 	nvkm_wr32(device, 0x400868, vramsz - 1);
365 
366 	/* interesting.. the below overwrites some of the tile setup above.. */
367 	nvkm_wr32(device, 0x400B20, 0x00000000);
368 	nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);
369 
370 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
371 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
372 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
373 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
374 	return 0;
375 }
376 
377 struct nvkm_oclass
378 nv20_gr_oclass = {
379 	.handle = NV_ENGINE(GR, 0x20),
380 	.ofuncs = &(struct nvkm_ofuncs) {
381 		.ctor = nv20_gr_ctor,
382 		.dtor = nv20_gr_dtor,
383 		.init = nv20_gr_init,
384 		.fini = _nvkm_gr_fini,
385 	},
386 };
387