1 // SPDX-License-Identifier: MIT
2 #include "nv20.h"
3 #include "regs.h"
4 
5 #include <core/client.h>
6 #include <core/gpuobj.h>
7 #include <engine/fifo.h>
8 #include <engine/fifo/chan.h>
9 #include <subdev/fb.h>
10 #include <subdev/timer.h>
11 
12 /*******************************************************************************
13  * PGRAPH context
14  ******************************************************************************/
15 
16 int
17 nv20_gr_chan_init(struct nvkm_object *object)
18 {
19 	struct nv20_gr_chan *chan = nv20_gr_chan(object);
20 	struct nv20_gr *gr = chan->gr;
21 	u32 inst = nvkm_memory_addr(chan->inst);
22 
23 	nvkm_kmap(gr->ctxtab);
24 	nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
25 	nvkm_done(gr->ctxtab);
26 	return 0;
27 }
28 
29 int
30 nv20_gr_chan_fini(struct nvkm_object *object, bool suspend)
31 {
32 	struct nv20_gr_chan *chan = nv20_gr_chan(object);
33 	struct nv20_gr *gr = chan->gr;
34 	struct nvkm_device *device = gr->base.engine.subdev.device;
35 	u32 inst = nvkm_memory_addr(chan->inst);
36 	int chid = -1;
37 
38 	nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
39 	if (nvkm_rd32(device, 0x400144) & 0x00010000)
40 		chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
41 	if (chan->chid == chid) {
42 		nvkm_wr32(device, 0x400784, inst >> 4);
43 		nvkm_wr32(device, 0x400788, 0x00000002);
44 		nvkm_msec(device, 2000,
45 			if (!nvkm_rd32(device, 0x400700))
46 				break;
47 		);
48 		nvkm_wr32(device, 0x400144, 0x10000000);
49 		nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
50 	}
51 	nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
52 
53 	nvkm_kmap(gr->ctxtab);
54 	nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
55 	nvkm_done(gr->ctxtab);
56 	return 0;
57 }
58 
59 void *
60 nv20_gr_chan_dtor(struct nvkm_object *object)
61 {
62 	struct nv20_gr_chan *chan = nv20_gr_chan(object);
63 	nvkm_memory_unref(&chan->inst);
64 	return chan;
65 }
66 
67 static const struct nvkm_object_func
68 nv20_gr_chan = {
69 	.dtor = nv20_gr_chan_dtor,
70 	.init = nv20_gr_chan_init,
71 	.fini = nv20_gr_chan_fini,
72 };
73 
74 static int
75 nv20_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
76 		 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
77 {
78 	struct nv20_gr *gr = nv20_gr(base);
79 	struct nv20_gr_chan *chan;
80 	int ret, i;
81 
82 	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
83 		return -ENOMEM;
84 	nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object);
85 	chan->gr = gr;
86 	chan->chid = fifoch->chid;
87 	*pobject = &chan->object;
88 
89 	ret = nvkm_memory_new(gr->base.engine.subdev.device,
90 			      NVKM_MEM_TARGET_INST, 0x37f0, 16, true,
91 			      &chan->inst);
92 	if (ret)
93 		return ret;
94 
95 	nvkm_kmap(chan->inst);
96 	nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
97 	nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
98 	nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
99 	nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
100 	nvkm_wo32(chan->inst, 0x047c, 0x00000101);
101 	nvkm_wo32(chan->inst, 0x0490, 0x00000111);
102 	nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
103 	for (i = 0x04d4; i <= 0x04e0; i += 4)
104 		nvkm_wo32(chan->inst, i, 0x00030303);
105 	for (i = 0x04f4; i <= 0x0500; i += 4)
106 		nvkm_wo32(chan->inst, i, 0x00080000);
107 	for (i = 0x050c; i <= 0x0518; i += 4)
108 		nvkm_wo32(chan->inst, i, 0x01012000);
109 	for (i = 0x051c; i <= 0x0528; i += 4)
110 		nvkm_wo32(chan->inst, i, 0x000105b8);
111 	for (i = 0x052c; i <= 0x0538; i += 4)
112 		nvkm_wo32(chan->inst, i, 0x00080008);
113 	for (i = 0x055c; i <= 0x0598; i += 4)
114 		nvkm_wo32(chan->inst, i, 0x07ff0000);
115 	nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
116 	nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
117 	nvkm_wo32(chan->inst, 0x0604, 0x00004000);
118 	nvkm_wo32(chan->inst, 0x0610, 0x00000001);
119 	nvkm_wo32(chan->inst, 0x0618, 0x00040000);
120 	nvkm_wo32(chan->inst, 0x061c, 0x00010000);
121 	for (i = 0x1c1c; i <= 0x248c; i += 16) {
122 		nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
123 		nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
124 		nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
125 	}
126 	nvkm_wo32(chan->inst, 0x281c, 0x3f800000);
127 	nvkm_wo32(chan->inst, 0x2830, 0x3f800000);
128 	nvkm_wo32(chan->inst, 0x285c, 0x40000000);
129 	nvkm_wo32(chan->inst, 0x2860, 0x3f800000);
130 	nvkm_wo32(chan->inst, 0x2864, 0x3f000000);
131 	nvkm_wo32(chan->inst, 0x286c, 0x40000000);
132 	nvkm_wo32(chan->inst, 0x2870, 0x3f800000);
133 	nvkm_wo32(chan->inst, 0x2878, 0xbf800000);
134 	nvkm_wo32(chan->inst, 0x2880, 0xbf800000);
135 	nvkm_wo32(chan->inst, 0x34a4, 0x000fe000);
136 	nvkm_wo32(chan->inst, 0x3530, 0x000003f8);
137 	nvkm_wo32(chan->inst, 0x3540, 0x002fe000);
138 	for (i = 0x355c; i <= 0x3578; i += 4)
139 		nvkm_wo32(chan->inst, i, 0x001c527c);
140 	nvkm_done(chan->inst);
141 	return 0;
142 }
143 
144 /*******************************************************************************
145  * PGRAPH engine/subdev functions
146  ******************************************************************************/
147 
148 void
149 nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
150 {
151 	struct nv20_gr *gr = nv20_gr(base);
152 	struct nvkm_device *device = gr->base.engine.subdev.device;
153 	struct nvkm_fifo *fifo = device->fifo;
154 	unsigned long flags;
155 
156 	nvkm_fifo_pause(fifo, &flags);
157 	nv04_gr_idle(&gr->base);
158 
159 	nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
160 	nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
161 	nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
162 
163 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
164 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
165 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
166 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
167 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
168 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
169 
170 	if (device->chipset != 0x34) {
171 		nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
172 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
173 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
174 	}
175 
176 	nvkm_fifo_start(fifo, &flags);
177 }
178 
179 void
180 nv20_gr_intr(struct nvkm_gr *base)
181 {
182 	struct nv20_gr *gr = nv20_gr(base);
183 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
184 	struct nvkm_device *device = subdev->device;
185 	struct nvkm_fifo_chan *chan;
186 	u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
187 	u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
188 	u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
189 	u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
190 	u32 chid = (addr & 0x01f00000) >> 20;
191 	u32 subc = (addr & 0x00070000) >> 16;
192 	u32 mthd = (addr & 0x00001ffc);
193 	u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
194 	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
195 	u32 show = stat;
196 	char msg[128], src[128], sta[128];
197 	unsigned long flags;
198 
199 	chan = nvkm_fifo_chan_chid(device->fifo, chid, &flags);
200 
201 	nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
202 	nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
203 
204 	if (show) {
205 		nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
206 		nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
207 		nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
208 		nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
209 				   "nstatus %08x [%s] ch %d [%s] subc %d "
210 				   "class %04x mthd %04x data %08x\n",
211 			   show, msg, nsource, src, nstatus, sta, chid,
212 			   chan ? chan->object.client->name : "unknown",
213 			   subc, class, mthd, data);
214 	}
215 
216 	nvkm_fifo_chan_put(device->fifo, flags, &chan);
217 }
218 
219 int
220 nv20_gr_oneinit(struct nvkm_gr *base)
221 {
222 	struct nv20_gr *gr = nv20_gr(base);
223 	return nvkm_memory_new(gr->base.engine.subdev.device,
224 			       NVKM_MEM_TARGET_INST, 32 * 4, 16,
225 			       true, &gr->ctxtab);
226 }
227 
228 int
229 nv20_gr_init(struct nvkm_gr *base)
230 {
231 	struct nv20_gr *gr = nv20_gr(base);
232 	struct nvkm_device *device = gr->base.engine.subdev.device;
233 	u32 tmp, vramsz;
234 	int i;
235 
236 	nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
237 			  nvkm_memory_addr(gr->ctxtab) >> 4);
238 
239 	if (device->chipset == 0x20) {
240 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
241 		for (i = 0; i < 15; i++)
242 			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
243 		nvkm_msec(device, 2000,
244 			if (!nvkm_rd32(device, 0x400700))
245 				break;
246 		);
247 	} else {
248 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
249 		for (i = 0; i < 32; i++)
250 			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
251 		nvkm_msec(device, 2000,
252 			if (!nvkm_rd32(device, 0x400700))
253 				break;
254 		);
255 	}
256 
257 	nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
258 	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
259 
260 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
261 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
262 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
263 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
264 	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
265 	nvkm_wr32(device, 0x40009C           , 0x00000040);
266 
267 	if (device->chipset >= 0x25) {
268 		nvkm_wr32(device, 0x400890, 0x00a8cfff);
269 		nvkm_wr32(device, 0x400610, 0x304B1FB6);
270 		nvkm_wr32(device, 0x400B80, 0x1cbd3883);
271 		nvkm_wr32(device, 0x400B84, 0x44000000);
272 		nvkm_wr32(device, 0x400098, 0x40000080);
273 		nvkm_wr32(device, 0x400B88, 0x000000ff);
274 
275 	} else {
276 		nvkm_wr32(device, 0x400880, 0x0008c7df);
277 		nvkm_wr32(device, 0x400094, 0x00000005);
278 		nvkm_wr32(device, 0x400B80, 0x45eae20e);
279 		nvkm_wr32(device, 0x400B84, 0x24000000);
280 		nvkm_wr32(device, 0x400098, 0x00000040);
281 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
282 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
283 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
284 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
285 	}
286 
287 	nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
288 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
289 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));
290 
291 	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
292 	nvkm_wr32(device, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
293 
294 	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
295 	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
296 	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;
297 	nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
298 
299 	/* begin RAM config */
300 	vramsz = device->func->resource_size(device, 1) - 1;
301 	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
302 	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
303 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
304 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
305 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
306 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
307 	nvkm_wr32(device, 0x400820, 0);
308 	nvkm_wr32(device, 0x400824, 0);
309 	nvkm_wr32(device, 0x400864, vramsz - 1);
310 	nvkm_wr32(device, 0x400868, vramsz - 1);
311 
312 	/* interesting.. the below overwrites some of the tile setup above.. */
313 	nvkm_wr32(device, 0x400B20, 0x00000000);
314 	nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);
315 
316 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
317 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
318 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
319 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
320 	return 0;
321 }
322 
323 void *
324 nv20_gr_dtor(struct nvkm_gr *base)
325 {
326 	struct nv20_gr *gr = nv20_gr(base);
327 	nvkm_memory_unref(&gr->ctxtab);
328 	return gr;
329 }
330 
331 int
332 nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
333 	     int index, struct nvkm_gr **pgr)
334 {
335 	struct nv20_gr *gr;
336 
337 	if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
338 		return -ENOMEM;
339 	*pgr = &gr->base;
340 
341 	return nvkm_gr_ctor(func, device, index, true, &gr->base);
342 }
343 
344 static const struct nvkm_gr_func
345 nv20_gr = {
346 	.dtor = nv20_gr_dtor,
347 	.oneinit = nv20_gr_oneinit,
348 	.init = nv20_gr_init,
349 	.intr = nv20_gr_intr,
350 	.tile = nv20_gr_tile,
351 	.chan_new = nv20_gr_chan_new,
352 	.sclass = {
353 		{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
354 		{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
355 		{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
356 		{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
357 		{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
358 		{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
359 		{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
360 		{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
361 		{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
362 		{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
363 		{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
364 		{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
365 		{ -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */
366 		{ -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
367 		{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
368 		{}
369 	}
370 };
371 
372 int
373 nv20_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
374 {
375 	return nv20_gr_new_(&nv20_gr, device, index, pgr);
376 }
377