1 /*
2  * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20  * DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "gf100.h"
24 #include "ctxgf100.h"
25 
26 #include <nvif/class.h>
27 
28 static void
29 gp10b_gr_init_num_active_ltcs(struct gf100_gr *gr)
30 {
31 	struct nvkm_device *device = gr->base.engine.subdev.device;
32 
33 	nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
34 }
35 
36 static const struct gf100_gr_func
37 gp10b_gr = {
38 	.init = gp100_gr_init,
39 	.init_gpc_mmu = gm200_gr_init_gpc_mmu,
40 	.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
41 	.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
42 	.init_num_active_ltcs = gp10b_gr_init_num_active_ltcs,
43 	.rops = gm200_gr_rops,
44 	.ppc_nr = 1,
45 	.grctx = &gp102_grctx,
46 	.sclass = {
47 		{ -1, -1, FERMI_TWOD_A },
48 		{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
49 		{ -1, -1, PASCAL_A, &gf100_fermi },
50 		{ -1, -1, PASCAL_COMPUTE_A },
51 		{}
52 	}
53 };
54 
55 int
56 gp10b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
57 {
58 	return gm200_gr_new_(&gp10b_gr, device, index, pgr);
59 }
60