1 /*
2  * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20  * DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "gf100.h"
24 #include "ctxgf100.h"
25 
26 #include <nvif/class.h>
27 
28 static const struct gf100_gr_func
29 gp10b_gr = {
30 	.oneinit_tiles = gm200_gr_oneinit_tiles,
31 	.oneinit_sm_id = gm200_gr_oneinit_sm_id,
32 	.init = gf100_gr_init,
33 	.init_gpc_mmu = gm200_gr_init_gpc_mmu,
34 	.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
35 	.init_zcull = gf117_gr_init_zcull,
36 	.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
37 	.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
38 	.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
39 	.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
40 	.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
41 	.init_419cc0 = gf100_gr_init_419cc0,
42 	.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
43 	.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
44 	.init_504430 = gm107_gr_init_504430,
45 	.init_shader_exceptions = gp100_gr_init_shader_exceptions,
46 	.trap_mp = gf100_gr_trap_mp,
47 	.rops = gm200_gr_rops,
48 	.gpc_nr = 1,
49 	.tpc_nr = 2,
50 	.ppc_nr = 1,
51 	.grctx = &gp102_grctx,
52 	.zbc = &gp102_gr_zbc,
53 	.sclass = {
54 		{ -1, -1, FERMI_TWOD_A },
55 		{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
56 		{ -1, -1, PASCAL_A, &gf100_fermi },
57 		{ -1, -1, PASCAL_COMPUTE_A },
58 		{}
59 	}
60 };
61 
62 int
63 gp10b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
64 {
65 	return gm200_gr_new_(&gp10b_gr, device, index, pgr);
66 }
67